公开(公告)号：US09443731B1

公开(公告)日：2016-09-13

申请号：US14627501

申请日：2015-02-20

Applicant: Tokyo Electron Limited

Inventor： David L. O'Meara ,  Angelique D. Raley ,  Akiteru Ko ,  Kiyohito Ito

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01J37/32082 ,  H01J37/32192 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32105 ,  H01L21/32139

Abstract: Provided is a method for increasing pattern density on a substrate comprising a structure with a patterned layer with a first composition and a sidewall and a cap layer of a second composition formed atop said structure. The sidewall is exposed to a chemical environment and creates a chemically modified sidewall layer of a third composition. The cap layer and an interior, non-modified portion of said structure is removed using an etching process to leave behind said chemically modified sidewall layer. A pattern transfer etch of said sidewall chemically modified layer onto the underlying layer of said substrate is performed. One or more integration operating variables are controlled to achieve target critical dimensions comprising width, height, sidewall angle, line width roughness, and/or line edge roughness of said structure.

Abstract translation: 提供了一种用于增加衬底上的图案密度的方法，其包括具有第一组成的图案层的结构，以及形成在所述结构顶部的侧壁和第二组合物的盖层。 侧壁暴露于化学环境并产生第三组合物的化学改性的侧壁层。 使用蚀刻工艺除去所述结构的盖层和内部未改性部分，以留下所述化学改性的侧壁层。 执行所述侧壁化学改性层到所述衬底的下层上的图案转移蚀刻。 控制一个或多个集成操作变量以实现包括所述结构的宽度，高度，侧壁角度，线宽粗糙度和/或线边缘粗糙度的目标临界尺寸。

公开(公告)号：US20160247680A1

公开(公告)日：2016-08-25

申请号：US14627501

申请日：2015-02-20

Applicant: Tokyo Electron Limited

Inventor： David L. O'Meara ,  Angelique D. Raley ,  Akiteru Ko ,  Kiyohito Ito

IPC: H01L21/033 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01J37/32082 ,  H01J37/32192 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32105 ,  H01L21/32139

Abstract: Provided is a method for increasing pattern density on a substrate comprising a structure with a patterned layer with a first composition and a sidewall and a cap layer of a second composition formed atop said structure. The sidewall is exposed to a chemical environment and creates a chemically modified sidewall layer of a third composition. The cap layer and an interior, non-modified portion of said structure is removed using an etching process to leave behind said chemically modified sidewall layer. A pattern transfer etch of said sidewall chemically modified layer onto the underlying layer of said substrate is performed. One or more integration operating variables are controlled to achieve target critical dimensions comprising width, height, sidewall angle, line width roughness, and/or line edge roughness of said structure.

Abstract translation: 提供了一种用于增加衬底上的图案密度的方法，其包括具有第一组成的图案层的结构，以及形成在所述结构顶部的侧壁和第二组合物的盖层。 侧壁暴露于化学环境并产生第三组合物的化学改性的侧壁层。 使用蚀刻工艺除去所述结构的盖层和内部未改性部分，以留下所述化学改性的侧壁层。 执行所述侧壁化学改性层到所述衬底的下层上的图案转移蚀刻。 控制一个或多个集成操作变量以实现包括所述结构的宽度，高度，侧壁角度，线宽粗糙度和/或线边缘粗糙度的目标临界尺寸。

公开(公告)号：US20160225640A1

公开(公告)日：2016-08-04

申请号：US15009013

申请日：2016-01-28

Applicant: Tokyo Electron Limited

Inventor： Angelique Raley ,  Akiteru Ko

IPC: H01L21/311

CPC classification number: H01L21/31144 ,  H01J37/32082 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/32137

Abstract: Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme comprising: providing a substrate having a patterned layer comprising a first mandrel and an underlying layer; performing a first conformal spacer deposition creating a first conformal layer; performing a first spacer reactive ion etch (RIE) process on the first conformal layer, creating a first spacer pattern; performing a first mandrel pull removing the first mandrel; performing a second conformal spacer deposition creating a second conformal layer; performing a second RIE process creating a second spacer pattern, the first spacer pattern acting as a second mandrel; performing a second mandrel pull process removing the first spacer pattern; and transferring the second spacer pattern into the underlying layer; where the integration targets include patterning uniformity, pulldown of structures, slimming of structures, and gouging of the underlying layer.

Abstract translation: 提供了一种使用积分方案来提高衬底上的结构的图案密度的方法，包括：提供具有包括第一心轴和下层的图案化层的衬底; 执行产生第一共形层的第一共形间隔物沉积; 在第一共形层上执行第一间隔反应离子蚀刻（RIE）工艺，产生第一间隔图案; 执行去除第一心轴的第一心轴拉动; 执行产生第二共形层的第二共形间隔物沉积; 执行产生第二间隔图案的第二RIE处理，所述第一间隔图案用作第二心轴; 执行去除所述第一间隔图案的第二芯棒拉拔工艺; 并将第二间隔图案转移到下面的层中; 其中整合目标包括图案均匀性，结构的下拉，结构的减薄和下层的气刨。

公开(公告)号：US20160020108A1

公开(公告)日：2016-01-21

申请号：US14869330

申请日：2015-09-29

Applicant: Tokyo Electron Limited

Inventor： Alok Ranjan ,  Akiteru Ko

IPC: H01L21/3065

CPC classification number: H01L21/3065 ,  H01J37/32082 ,  H01J37/3211 ,  H01J37/32137 ,  H01J37/32146 ,  H01J37/32165 ,  H01J37/3222 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32697 ,  H01J37/32706 ,  H01J2237/334 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/67069 ,  H01L21/6831 ,  H01L29/517 ,  H01L29/518

Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).

公开(公告)号：US08980111B2

公开(公告)日：2015-03-17

申请号：US13893917

申请日：2013-05-14

Applicant: Tokyo Electron Limited

Inventor： Akiteru Ko ,  Kosuke Ogasawara

IPC: C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  B44C1/22 ,  H01L21/302 ,  H01L21/461 ,  H01L21/311 ,  G03F7/36

CPC classification number: G03F7/36 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method for patterning a substrate is described. The patterning method may include conformally depositing a material layer over a pattern according to a conformal deposition process, selectively depositing a second material layer on an exposed surface of the material layer according to a selected deposition process recipe; partially removing the material layer using a plasma etching process to expose a top surface of the pattern, open a portion of the material layer at a bottom region between adjacent features of the pattern, and retain a remaining portion of the material layer on sidewalls of the pattern; and removing the pattern using one or more etching processes to leave a final pattern comprising the remaining portion of the material layer and the second layer.

Abstract translation: 描述了用于图案化衬底的方法。 图案化方法可以包括根据保形沉积工艺在图案上共形沉积材料层，根据所选择的沉积工艺配方在材料层的暴露表面上选择性地沉积第二材料层; 使用等离子体蚀刻工艺部分地去除材料层以暴露图案的顶表面，在图案的相邻特征之间的底部区域处打开材料层的一部分，并且将材料层的剩余部分保留在所述图案的侧壁上 模式; 以及使用一个或多个蚀刻工艺去除图案以留下包括材料层和第二层的剩余部分的最终图案。

公开(公告)号：US20240339309A1

公开(公告)日：2024-10-10

申请号：US18298259

申请日：2023-04-10

Applicant: Tokyo Electron Limited

Inventor： Sergey Voronin ,  Francisco Machuca ,  Blaze Messer ,  Yan Chen ,  Ying Zhu ,  Mihail Mihaylov ,  Joel Ng ,  Ashawaraya Shalini ,  Da Song ,  Akiteru Ko

IPC: H01J37/32 ,  H01J37/18

CPC classification number: H01J37/32972 ,  H01J37/18 ,  H01J37/32357 ,  H01J37/32963 ,  H01J2237/3343

Abstract: A processing system that includes: a processing chamber configured to hold a substrate to be processed; a first vacuum pump; a second vacuum pump disposed downstream from the first vacuum pump; an exhaust gas line connecting the process chamber and the first vacuum pump, and the first vacuum pump and the second vacuum pump; a plasma power supply including a first RF power source configured to generate a plasma from a portion of an exhaust gas between the first and second vacuum pumps; and an optical emission spectroscopy (OES) measurement assembly including an OES detector configured to measure OES signals from the plasma.

公开(公告)号：US20240053684A1

公开(公告)日：2024-02-15

申请号：US17888135

申请日：2022-08-15

Applicant: Tokyo Electron Limited

Inventor： Hamed Hajibabaeinajafabadi ,  Akiteru Ko ,  Yu-Hao Tsai ,  Sergey Voronin

IPC: G03F7/36 ,  H01L21/308

CPC classification number: G03F7/36 ,  H01L21/3086

Abstract: A method of processing a substrate includes receiving a substrate including a photoresist film including exposed and unexposed portions, etching parts of the unexposed portions of the photoresist film with a developing gas in a process chamber to leave a residual part of the unexposed portions, and purging the developing gas from the process chamber with a purging gas. After purging the developing gas, the residual part of the unexposed portions is etched with the developing gas. The substrate is etched using exposed portions of the photoresist film as a mask.

公开(公告)号：US11615958B2

公开(公告)日：2023-03-28

申请号：US16827928

申请日：2020-03-24

Applicant: Tokyo Electron Limited

Inventor： Akiteru Ko

IPC: H01L21/033 ,  G02B1/11 ,  G03F7/20 ,  G02B1/14

Abstract: Embodiments reduce or eliminate microbridge defects in extreme ultraviolet (EUV) patterning for microelectronic workpieces. A patterned layer is formed over a multilayer structure using an EUV patterning process. Protective material is then deposited over the patterned layer using one or more oblique deposition processes. One or more material bridges extending between line patterns within the patterned layer are then removed while using the protective material to protect the line patterns. As such, microbridge defects caused in prior solutions are reduced or eliminated. For one embodiment, the oblique deposition processes include physical vapor deposition (PVD) processes that apply the same or different protective materials in multiple directions with respect to line patterns within the patterned layer. For one embodiment, the removing includes one or more plasma trim processes. Variations can be implemented.

公开(公告)号：US11551930B2

公开(公告)日：2023-01-10

申请号：US16299623

申请日：2019-03-12

Applicant: Tokyo Electron Limited

Inventor： Akiteru Ko ,  Kazuya Okubo ,  Hiroyuki Toshima

IPC: H01L21/00 ,  H01L21/033 ,  H01L21/311 ,  H01L21/02

Abstract: Embodiments are described herein to reshape spacer profiles to improve spacer uniformity and thereby improve etch uniformity during pattern transfer associated with self-aligned multiple-patterning (SAMP) processes. For disclosed embodiments, cores are formed on a material layer for a substrate of a microelectronic workpiece. A spacer material layer is then formed over the cores. Symmetric spacers are then formed adjacent the cores by reshaping the spacer material layer using one or more directional deposition processes to deposit additional spacer material and using one or more etch process steps. For one example embodiment, one or more oblique physical vapor deposition (PVD) processes are used to deposit the additional spacer material for the spacer profile reshaping. This reshaping of the spacer profiles allows for symmetric spacers to be formed thereby improving etch uniformity during subsequent pattern transfer processes.

公开(公告)号：US20210343586A1

公开(公告)日：2021-11-04

申请号：US16864472

申请日：2020-05-01

Applicant: Tokyo Electron Limited

Inventor： Hirokazu Aizawa ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/768

Abstract: A self-aligned multiple patterning (SAMP) multi-color spacer patterning process is disclosed for formation of structures on substrates. Trenches and vias may be formed in the process. A trench memorization layer and a via memorization layer may be formed on the substrate. In one embodiment, the trench memorization layer and the via memorization layer are formed between the multi-color spacer patterning structures and a low-k interlayer dielectric layer. The use of the trench memorization layer and the via memorization layer allows the formation of trenches and vias in the low-k interlayer dielectric layer without causing damage to the low-k properties of the low-k interlayer dielectric layer.