公开(公告)号：US20180314773A1

公开(公告)日：2018-11-01

申请号：US15497489

申请日：2017-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ching Cheng ,  Chun-Liang Hou ,  Chien-Hung Chen ,  Wen-Jung Liao ,  Min-Chin Hsieh ,  Da-Ching Liao ,  Li-Chin Wang

IPC: G06F17/50

Abstract: A method for analyzing a process output and a method for creating an equipment parameter model are provided. The method for analyzing the process output includes the following steps: A plurality of process steps are obtained. A processor obtains a step model set including a plurality of first step regression models, each of which represents a relationship between N of the process steps and a process output. The processor calculates a correlation of each of the first step regression models. The processor picks up at least two of the first step regression models to be a plurality of second step regression models whose correlations are ranked at top among the correlations of the first step regression models. The processor updates the step model set by a plurality of third step regression models, each of which represents a relationship between M of the process steps and the process output.

公开(公告)号：US10068909B1

公开(公告)日：2018-09-04

申请号：US15795270

申请日：2017-10-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Chien-Hung Chen

IPC: G11C11/412 ,  G11C11/40 ,  H01L27/11 ,  H01L27/02 ,  H01L23/528 ,  G11C11/419 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088

Abstract: The present invention provides a layout pattern of a memory device composed of static random access memory (SRAM), comprising four memory units located on a substrate, each memory unit being located in a non-rectangular region, the four non-rectangular regions combine a rectangular region, wherein each memory unit comprises a first inverter comprising a first pull-up transistor (PL1) and a first pull-down transistor (PD1), a second inverter comprises a second pull-up transistor (PL2) and a second pull-down transistor (PD2), an access transistor (PG) and a switching transistor (SW), wherein the source of the PG is coupled to an input terminal of the first inverter and a drain of the SW, a source of the SW is coupled to an output of the second inverter, wherein the PD1, the PD2, the SW, and the PG comprise a first diffusion region, the PL1 and the PL2 comprise a second diffusion region.

公开(公告)号：US20180053826A1

公开(公告)日：2018-02-22

申请号：US15797011

申请日：2017-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L29/165 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US09508835B2

公开(公告)日：2016-11-29

申请号：US13741399

申请日：2013-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chung Chang ,  Shen-De Wang ,  Ya-Huei Huang ,  Feng-Ji Tsai ,  Chien-Hung Chen

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/4234 ,  H01L29/792

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.

Abstract translation: 一种用于制造非易失性存储器结构的方法包括提供具有存储区域和限定在其上的逻辑区域的衬底，在形成存储区域中的至少第一栅极的同时屏蔽逻辑区域，形成氧化物 - 氧化物 - 氧化物（ONO ）结构，在衬底上形成覆盖ONO结构的氧化物结构，在逻辑区域中形成第二栅极的同时掩蔽存储区域，以及在第一栅极的侧壁上形成第一间隔物，在侧壁上形成第二间隔物 的第二个门。

公开(公告)号：US09508734B2

公开(公告)日：2016-11-29

申请号：US15077892

申请日：2016-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Sheng Yang ,  Chien-Hung Chen

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.

Abstract translation: 公开了一种氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）器件。 SONOS器件包括衬底; 衬底上的第一氧化物层; 在所述第一氧化物层上的富硅捕获层; 富硅捕获层上的含氮层; 含氮层上的富氧氧化物层; 和富硅氧化物层上的多晶硅层。

公开(公告)号：US20160204121A1

公开(公告)日：2016-07-14

申请号：US15077892

申请日：2016-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Sheng Yang ,  Chien-Hung Chen

IPC: H01L27/115 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.

Abstract translation: 公开了一种氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）器件。 SONOS器件包括衬底; 衬底上的第一氧化物层; 在所述第一氧化物层上的富硅捕获层; 富硅捕获层上的含氮层; 含氮层上的富硅氧化物层; 和富硅氧化物层上的多晶硅层。

公开(公告)号：US09147035B1

公开(公告)日：2015-09-29

申请号：US14533471

申请日：2014-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsun Huang ,  Chao-Yao Chiang ,  Chien-Hung Chen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70

Abstract: A verifying method of an optical proximity correction is provided. The verifying method includes the following steps. A first netlist file is extracted from an integrated pre-OPC layout. A first post-OPC layout and a second post-OPC layout are merged to be an integrated post-OPC layout. A second netlist file is extracted from the integrated post-OPC layout. The first netlist file and the second netlist are compared.

Abstract translation: 提供了光学邻近校正的验证方法。 验证方法包括以下步骤。 从集成的前OPC布局中提取第一个网表文件。 第一个后OPC布局和第二个后OPC布局被合并为一个集成的OPC后布局。 从集成的后OPC布局中提取第二个网表文件。 比较第一个网表文件和第二个网表。

公开(公告)号：US20250113488A1

公开(公告)日：2025-04-03

申请号：US18494747

申请日：2023-10-25

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Ling Hsiu Chou ,  Jen Yang Hsueh ,  Chih-Yang Hsu

IPC: H10B43/30

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes a substrate having first and second regions, first and second isolation structures in the substrate, a charge storage layer on the substrate, first and second gates and doped regions. The first isolation structures define first active areas in the first region. A top surface of the first isolation structure is higher than that of the substrate. The second isolation structures define second active areas in the second region. A top surface of the second isolation structure is lower than that of the substrate. The first gate is on the charge storage layer in the first active area. The second gate is on the charge storage layer in the second active area. The doped regions are in the substrate at two sides of the first gate and at two sides of the second gate.

公开(公告)号：US12119053B2

公开(公告)日：2024-10-15

申请号：US17680264

申请日：2022-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Jen-Yang Hsueh ,  Ling-Hsiu Chou ,  Chih-Yang Hsu

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/0483

Abstract: When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

公开(公告)号：US20240114688A1

公开(公告)日：2024-04-04

申请号：US17990738

申请日：2022-11-21

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Chien-Hung Chen ,  Chia-Hui Huang ,  Ling Hsiu Chou ,  Jen Yang Hsueh ,  Chih-Yang Hsu

IPC: H10B43/30 ,  H10B41/30

CPC classification number: H01L27/11568 ,  H01L27/11521

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.