公开(公告)号：US09184292B2

公开(公告)日：2015-11-10

申请号：US14340267

申请日：2014-07-24

Applicant: United Microelectronics Corp.

Inventor： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chun-Yuan Wu ,  Teng-Chun Tsai ,  Chih-Chien Liu

IPC: H01L29/04 ,  H01L29/76 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/66 ,  H01L21/764 ,  H01L29/165 ,  H01L21/311 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/314 ,  H01L21/318 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.

Abstract translation: 描述用于形成FinFET的半导体结构。 半导体结构包括半导体衬底，衬底上的FinFET的多个奇数鳍片，以及FinFET的奇数鳍片之间的衬底上的FinFET的多个偶数鳍片。 FinFET的奇数鳍从衬底定义。 FinFET的均匀鳍片与宽度和材料中的至少一个中的FinFET的奇数鳍不同，并且可以与FinFET的高度的奇数鳍不同。

公开(公告)号：US08841193B2

公开(公告)日：2014-09-23

申请号：US13928366

申请日：2013-06-26

Applicant: United Microelectronics Corp.

Inventor： Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Shu-Yen Chan ,  Ling-Chun Chou ,  Tsung-Hung Chang ,  Chun-Yuan Wu

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7847

Abstract: A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer.

Abstract translation: 公开了一种包括衬底和设置在衬底上的栅极结构的半导体结构。 栅极结构包括设置在基板上的栅极介质层，设置在栅极介电层上的栅极材料层和具有矩形横截面的外部间隔物。 外隔离物的顶表面比栅极材料层的顶表面低。

公开(公告)号：US08476164B1

公开(公告)日：2013-07-02

申请号：US13661111

申请日：2012-10-26

Applicant: United Microelectronics Corp.

Inventor： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chih-Chien Liu ,  Chia-Lin Hsu ,  Chun-Yuan Wu

IPC: H01L21/44

CPC classification number: H01L29/665 ,  H01L29/78 ,  H01L29/7845

Abstract: A method of manufacturing semiconductor device is provided. A substrate at least with a patterned silicon-containing layer on the substrate and spacers adjacent to the patterned silicon-containing layer is provided. A metal layer is formed on the substrate and covers the patterned silicon-containing layer and spacers. Then, a capping layer is formed on the metal layer. A first rapid thermal process is performed to at least make a portion of the metal layer react with the substrate around the spacers to form transitional silicides. The capping layer and the unreacted portions of the metal layer are removed. A first nitride film with a first tensile stress S1 is formed on the substrate. A second rapid thermal process is performed to transfer the transitional silicide to a silicide and transfer the first nitride film to a second nitride film with a second tensile stress S2, wherein S2>S1.

Abstract translation: 提供一种制造半导体器件的方法。 提供至少在衬底上具有图案化的含硅层的衬底和与图案化的含硅层相邻的衬垫。 在基板上形成金属层，并覆盖图案化的含硅层和间隔物。 然后，在金属层上形成覆盖层。 进行第一快速热处理以至少使金属层的一部分与衬垫周围的衬底反应以形成过渡的硅化物。 除去覆盖层和金属层的未反应部分。 在基板上形成具有第一拉伸应力S1的第一氮化物膜。 执行第二快速热处理以将过渡硅化物转移到硅化物，并将第一氮化物膜转移到具有第二拉伸应力S2的第二氮化物膜，其中S2> S1。

公开(公告)号：US10177231B2

公开(公告)日：2019-01-08

申请号：US15797011

申请日：2017-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L29/165 ,  H01L21/3065

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US20180226435A1

公开(公告)日：2018-08-09

申请号：US15947853

申请日：2018-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Fu Hsu ,  Chun-Yuan Wu

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L29/51 ,  H01L29/24 ,  H01L21/02 ,  H01L23/528 ,  H01L21/768 ,  H01L21/441

CPC classification number: H01L27/1237 ,  H01L21/02107 ,  H01L21/02323 ,  H01L21/02565 ,  H01L21/441 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/512 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present invention provides a method of forming a semiconductor device. First, a substrate having a first insulating layer formed thereon is provided. After forming an oxide semiconductor layer on the first insulating layer, two source/drain regions are formed on the oxide semiconductor layer. A bottom oxide layer is formed to entirely cover the source/drain regions, following by forming a high-k dielectric layer on the bottom oxide layer. Next, a thermal process is performed on the high-k dielectric layer, and a plasma treatment is performed on the high-k dielectric layer in the presence of a gas containing an oxygen element

公开(公告)号：US09991337B2

公开(公告)日：2018-06-05

申请号：US14840038

申请日：2015-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chun-Yuan Wu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/308 ,  H01L21/311 ,  H01L21/283

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76232 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.

公开(公告)号：US20180130871A1

公开(公告)日：2018-05-10

申请号：US15346717

申请日：2016-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC: H01L49/02

CPC classification number: H01L28/88

Abstract: The present invention provides a capacitor structure, including a bottom plate and a top plate, wherein the top plate has a first sidewall, and wherein an area of the top plate is less than an area of the bottom plate. The capacitor structure further includes a dielectric layer in between the bottom plate and the top plate, the dielectric layer having a second sidewall, wherein the first sidewall is aligned with the second sidewall, and at least one sidewall spacer placed against the first sidewall of the top plate and the second sidewall of the dielectric layer, and overlaying a portion of the bottom plate.

公开(公告)号：US09837493B2

公开(公告)日：2017-12-05

申请号：US14940867

申请日：2015-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US09673053B2

公开(公告)日：2017-06-06

申请号：US14549529

申请日：2014-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rung-Yuan Lee ,  Yu-Ting Li ,  Jing-Yin Jhang ,  Chen-Yi Weng ,  Jia-Feng Fang ,  Yi-Wei Chen ,  Wei-Jen Wu ,  Po-Cheng Huang ,  Fu-Shou Tsai ,  Kun-Ju Li ,  Wen-Chin Lin ,  Chih-Chien Liu ,  Chih-Hsun Lin ,  Chun-Yuan Wu

IPC: H01L21/306 ,  H01L21/28

CPC classification number: H01L21/30625 ,  H01L21/28123 ,  H01L21/32115 ,  H01L21/3212

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first material layer on the substrate; forming a stop layer on the first material layer; forming a second material layer on the stop layer; and performing a planarizing process to remove the second material layer, the stop layer, and part of the first material layer for forming a gate layer.

公开(公告)号：US20170117414A1

公开(公告)日：2017-04-27

申请号：US14941674

申请日：2015-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Kun-Hsin Chen ,  Tien-I Wu ,  Yu-Ru Yang ,  Huai-Tzu Chiang

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/167 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: A semiconductor structure including a semiconductor substrate and at least a fin structure formed thereon. The semiconductor substrate includes a first semiconductor material. The fin structure includes a first epitaxial layer and a second epitaxial layer formed between the first epitaxial layer and the semiconductor substrate. The first epitaxial layer includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The second epitaxial layer includes the first semiconductor material and the second semiconductor material. The second epitaxial layer further includes conductive dopants.