公开(公告)号：US20100001268A1

公开(公告)日：2010-01-07

申请号：US12167039

申请日：2008-07-02

Applicant: Robert C. Frye ,  Kai Liu ,  Yaojian Lin

Inventor： Robert C. Frye ,  Kai Liu ,  Yaojian Lin

IPC: H01L23/58 ,  H01L21/02

CPC classification number: H01L22/34 ,  H01L23/64 ,  H01L28/10 ,  H01L28/40 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/3011 ,  H01L2924/00014

Abstract: A semiconductor device has an inductor and capacitor formed on the substrate. The inductor and capacitor are electrically connected in series. The inductor is a coiled conductive layer. The capacitor has first and second conductive layers separated by an insulating layer. A first test pad and second test pad are formed on the substrate. A terminal of the inductor is coupled to the first and second test pads. A third test pad and fourth test pad are formed on the substrate. A terminal of the capacitor is coupled to the third and fourth test pads such that the inductor and capacitor are connected in shunt between the first and second test pads and the third and fourth test pads. An electrical characteristic of the inductor and capacitor such that resonant frequency and quality factor are tested using a two-port shunt measurement which negates series resistance of test probes.

Abstract translation: 半导体器件具有形成在衬底上的电感器和电容器。 电感器和电容器串联电连接。 电感器是线圈导电层。 该电容器具有被绝缘层隔开的第一和第二导电层。 在基板上形成第一测试焊盘和第二测试焊盘。 电感器的端子耦合到第一和第二测试焊盘。 在基板上形成第三测试焊盘和第四测试焊盘。 电容器的端子耦合到第三和第四测试焊盘，使得电感器和电容器在第一和第二测试焊盘与第三和第四测试焊盘之间分流连接。 电感器和电容器的电气特性使得谐振频率和品质因数使用双端口分流测量进行测试，这样可以消除测试探针的串联电阻。

公开(公告)号：US07566650B2

公开(公告)日：2009-07-28

申请号：US11162822

申请日：2005-09-23

Applicant: Yaojian Lin ,  Byung Tai Do ,  Romeo Emmanuel P. Alvarez

Inventor： Yaojian Lin ,  Byung Tai Do ,  Romeo Emmanuel P. Alvarez

IPC: H01L21/44 ,  H01L21/4763

CPC classification number: H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the openings therethrough. A second UBM layer of chromium/copper alloy is deposited on the first UBM layer. A third UBM layer of copper is deposited on the second UBM layer. UBM pads of at least two different sizes are formed from the UBM layers. Solder paste is printed over at least some of the UBM pads. The solder paste is reflowed to form at least smaller solder bumps on at least some of the UBM pads. Bigger solder bumps are formed on at least some of the UBM pads.

Abstract translation: 集成电路焊料凸块系统提供衬底并在衬底上形成再分布层。 在再分布层上形成绝缘层。 绝缘层具有穿过其中的多个开口。 第一UBM层钛沉积在绝缘层上和通过其中的开口中。 第二UBM层的铬/铜合金沉积在第一UBM层上。 铜的第三UBM层沉积在第二UBM层上。 具有至少两种不同尺寸的UBM焊盘由UBM层形成。 至少一些UBM垫上印有焊膏。 焊膏被回流以在至少一些UBM焊盘上形成至少较小的焊料凸块。 在至少一些UBM垫上形成更大的焊料凸块。

公开(公告)号：US20090170241A1

公开(公告)日：2009-07-02

申请号：US11964397

申请日：2007-12-26

Applicant: Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L21/56

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/82039 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/187 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by forming contact pads on a sacrificial carrier. The contact pads may be formed on a pillar. A semiconductor die is mounted to electrically connect to the contact pads with solder bumps or wire bonds. The semiconductor die is encapsulated with molding compound. The sacrificial carrier is removed. A backside interconnect structure has a first conductive layer formed over the molding compound to electrically connect to the contact pads. A first insulating layer is formed over the first conductive layer. A portion of the first insulating layer is removed to expose the first conductive layer. Solder material is deposited in electrical contact with the first conductive layer. The solder material is reflowed to form a solder bump. A wire bond electrically connects to a contact pad. A front-side interconnect structure can be formed through the molding compound to the contact pads.

Abstract translation: 通过在牺牲载体上形成接触垫来制造半导体器件。 接触垫可以形成在支柱上。 半导体管芯被安装成用焊料凸块或引线接合电连接到接触焊盘。 半导体管芯用模塑料封装。 牺牲载体被去除。 背面互连结构具有形成在模制化合物上的第一导电层以电连接到接触焊盘。 第一绝缘层形成在第一导电层上。 去除第一绝缘层的一部分以露出第一导电层。 焊料与第一导电层电接触沉积。 焊料材料被回流以形成焊料凸块。 导线键合电连接到接触垫。 可以通过模制化合物将前侧互连结构形成到接触垫。

公开(公告)号：US20090155959A1

公开(公告)日：2009-06-18

申请号：US11958603

申请日：2007-12-18

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

IPC: H01L21/50

CPC classification number: H01L23/50 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/20 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09736 ,  H05K2203/016 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing a semiconductor device includes providing a substrate with an insulation layer disposed on a top surface of the substrate, forming a passive device over the top surface of the substrate, removing the substrate, depositing an insulating polymer film layer over the insulation layer, and depositing a metal layer over the insulating polymer film layer. A solder mask can be formed over the metal layer. A conformal metal layer can then be formed over the solder mask. A notch can be formed in the insulation layer to enhance the connection between the insulating polymer film layer and the insulation layer. Additional semiconductor die can be electrically connected to the passive device. The substrate is removed by removing a first amount of the substrate using a back grind process, and then removing a second amount of the substrate using a wet dry, dry etch, or chemical-mechanical planarization process.

Abstract translation: 一种制造半导体器件的方法包括：在衬底的顶表面上设置绝缘层，在衬底的顶表面上形成无源器件，去除衬底，在绝缘层上沉积绝缘聚合物膜层 并且在绝缘聚合物膜层上沉积金属层。 可以在金属层上形成焊接掩模。 然后可以在焊接掩模上形成保形金属层。 可以在绝缘层中形成切口以增强绝缘聚合物膜层和绝缘层之间的连接。 另外的半导体管芯可以电连接到无源器件。 通过使用后研磨工艺去除第一量的基材，然后使用湿干，干蚀刻或化学机械平面化工艺除去第二量的基材来除去基材。

公开(公告)号：US20090140421A1

公开(公告)日：2009-06-04

申请号：US11949255

申请日：2007-12-03

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

IPC: H01L23/48 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L23/5389 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L27/1266 ,  H01L28/00 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has integrated passive circuit elements. A first substrate is formed on a backside of the semiconductor device. The passive circuit element is formed over the insulating layer. The passive circuit element can be an inductor, capacitor, or resistor. A passivation layer is formed over the passive circuit element. A carrier is attached to the passivation layer. The first substrate is removed. A non-silicon substrate is formed over the insulating layer on the backside of the semiconductor device. The non-silicon substrate is made with glass, molding compound, epoxy, polymer, or polymer composite. An adhesive layer is formed between the non-silicon substrate and insulating layer. A via is formed between the insulating layer and first passivation layer. The carrier is removed. An under bump metallization is formed over the passivation layer in electrical contact with the passive circuit element. A solder bump is formed on the under bump metallization.

Abstract translation: 半导体器件集成无源电路元件。 第一衬底形成在半导体器件的背面。 无源电路元件形成在绝缘层上。 无源电路元件可以是电感器，电容器或电阻器。 钝化层形成在无源电路元件上。 载体附着在钝化层上。 去除第一衬底。 在半导体器件的背面上的绝缘层上形成非硅衬底。 非硅衬底由玻璃，模塑料，环氧树脂，聚合物或聚合物复合材料制成。 在非硅衬底和绝缘层之间形成粘合剂层。 在绝缘层和第一钝化层之间形成通孔。 载体被移除。 在与无源电路元件电接触的钝化层之上形成凸起下金属化。 在凸块下方形成焊锡凸块。

公开(公告)号：US20090004504A1

公开(公告)日：2009-01-01

申请号：US11769296

申请日：2007-06-27

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang

IPC: B05D5/12 ,  H01L29/12

CPC classification number: H05K1/167 ,  H01L21/4846 ,  H01L23/49548 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/04941 ,  H05K3/467 ,  H05K2201/0195 ,  H05K2201/0317 ,  H05K2201/09436 ,  H05K2201/09672 ,  Y10T29/43 ,  Y10T428/12528 ,  H01L2224/05599

Abstract: A circuit system comprising: forming a lower electrode over a substrate; forming a resistive film over the lower electrode; forming a multi-layered insulating stack over a portion of the resistive film; and forming an upper electrode over a portion of the multi-layered insulating stack.

Abstract translation: 一种电路系统，包括：在衬底上形成下电极; 在下电极上形成电阻膜; 在所述电阻膜的一部分上形成多层绝缘堆叠; 以及在所述多层绝缘堆叠的一部分上形成上电极。

公开(公告)号：US07410824B2

公开(公告)日：2008-08-12

申请号：US11009436

申请日：2004-12-09

Applicant: Byung Tai Do ,  Romeo Emmanuel P. Alvarez ,  Yaojian Lin

Inventor： Byung Tai Do ,  Romeo Emmanuel P. Alvarez ,  Yaojian Lin

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/4763

CPC classification number: H05K3/3484 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K3/1216 ,  H05K3/3452 ,  H05K2203/043 ,  H05K2203/0568 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A method for solder bumping provides a substrate and forms a film on the substrate. The film has openings therethrough. A stencil is aligned on the film. The stencil has openings therethrough over the openings through the film. Solder paste is printed onto the substrate and into the openings through the stencil and the openings through the film. The solder paste is reflowed to form solder balls therefrom. The stencil and the film are then removed.

Abstract translation: 焊接凸块的方法提供基板并在基板上形成膜。 该膜具有开口。 模板在电影上对齐。 模板在穿过薄膜的开口上方具有穿过其的开口。 焊膏通过模版印刷到基板上并通过薄膜印刷到开口中。 焊膏被回流以从其形成焊球。 然后去除模板和胶片。

公开(公告)号：US20080150161A1

公开(公告)日：2008-06-26

申请号：US11934009

申请日：2007-11-01

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/013

Abstract: A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed over the passivation layer. A barrier layer is formed over the adhesive layer. A wetting layer is formed over the barrier layer. The barrier layer and wetting layer in a first region are removed, while the barrier layer, wetting layer, and adhesive layer in a second region are maintained. The adhesive layer over the passivation layer in the first region are maintained until the solder bumps are formed. By keeping the adhesive layer over the passivation layer until after formation of the solder bumps, less cracking occurs in the passivation layer.

Abstract translation: 倒装芯片半导体器件具有在其上形成有多个有源器件的衬底。 接触焊盘形成在与多个有源器件电接触的衬底上。 在衬底和中间导电层上形成钝化层。 在钝化层上形成粘合剂层。 在粘合剂层上形成阻挡层。 在阻挡层上形成润湿层。 去除第一区域中的阻挡层和润湿层，同时维持第二区域中的阻挡层，润湿层和粘合剂层。 保持第一区域中的钝化层上的粘合剂层直到形成焊料凸点。 通过将粘合剂层保持在钝化层上方直到形成焊料凸点，在钝化层中发生较少的破裂。

公开(公告)号：US10074553B2

公开(公告)日：2018-09-11

申请号：US11949282

申请日：2007-12-03

Applicant: Yaojian Lin

Inventor： Yaojian Lin

IPC: H01L21/683 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/6835 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48472 ,  H01L2224/81005 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a wafer level chip scale package, a wafer level interconnect structure is formed on a dummy substrate with temperatures in excess of 200° C. First semiconductor die are mounted on the wafer level interconnect structure. The wafer level interconnect structure provides a complete electrical interconnect between the semiconductor die and one or more of the solder bumps according to the function of the semiconductor device. A second semiconductor die can be mounted to the first semiconductor die. A first encapsulant is formed over the semiconductor die. A second encapsulant is formed over the first encapsulant. The dummy substrate is removed. A first UBM is formed in electrical contact with the first conductive layer. Solder bumps are made in electrical contact with the first UBM. A second UBM is formed to electrically connect the semiconductor die to the wafer level interconnect structure.

公开(公告)号：US09865482B2

公开(公告)日：2018-01-09

申请号：US13438696

申请日：2012-04-03

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) is mounted to the temporary carrier using an adhesive. The IPD includes a capacitor and a resistor and has a plurality of through-silicon vias (TSVs). A discrete component is mounted to the temporary carrier using the adhesive. The discrete component includes a capacitor. The IPD and the discrete component are encapsulated using a molding compound. A first metal layer is formed over the molding compound. The first metal layer is connected to the TSVs of the IPD and forms an inductor. The temporary carrier and the adhesive are removed, and a second metal layer is formed over the IPD and the discrete component. The second metal layer interconnects the IPD and the discrete component and forms an inductor. An optional interconnect structure is formed over the second metal layer.