公开(公告)号：US20190121711A1

公开(公告)日：2019-04-25

申请号：US16222624

申请日：2018-12-17

Applicant: SK hynix Inc.

Inventor： Joon-Woo KIM

IPC: G06F11/20 ,  G06F12/10 ,  G11C29/52 ,  G11C5/04 ,  G06F11/10

CPC classification number: G06F11/2094 ,  G06F11/1048 ,  G06F11/1068 ,  G06F12/0292 ,  G06F12/10 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2212/1032 ,  G11C5/04 ,  G11C29/52 ,  G11C29/70

Abstract: A memory module may include a first memory module comprising a plurality of first memory devices each having an extra memory region, a second memory module comprising a plurality of second memory devices each having an extra memory region, and a control logic suitable for writing/reading data to/from the first memory devices, wherein the control logic writes/reads target data to be transferred to/from a third memory device having an error among the first memory devices, to/from the extra memory regions of the second memory devices.

公开(公告)号：US20190121699A1

公开(公告)日：2019-04-25

申请号：US15790368

申请日：2017-10-23

Applicant: Western Digital Technologies, Inc.

Inventor： Inon COHEN ,  Asaf GUETA

IPC: G06F11/14

CPC classification number: G06F11/1438 ,  G06F11/1441 ,  G06F2201/805

Abstract: A method to perform a lossless synchronization software reset is disclosed including provisions for monitoring an arrangement for occurrence of a software reset condition; saving at least one arrangement parameter in a memory in the arrangement; performing at least one software reset on the arrangement; performing a device mount procedure; reading the at least one arrangement parameter in the memory and initializing at least one component according to the at least one arrangement parameter saved in the memory.

公开(公告)号：US20190089495A1

公开(公告)日：2019-03-21

申请号：US15708488

申请日：2017-09-19

Applicant: International Business Machines Corporation

Inventor： CHAD M. ALBERTSON ,  ERIC J. CAMPBELL ,  NICHOLAS J. OLLERICH ,  CHRISTOPHER W. STEFFEN ,  CURTIS C. WOLLBRINK

IPC: H04L1/20 ,  G06F11/00

CPC classification number: H04L1/201 ,  G06F11/006 ,  G06F13/00 ,  G06F13/4265 ,  G06F2201/805

Abstract: Low latency corrupt data tagging on a cross-chip link including receiving, from the cross-chip link, a control flit comprising a virtual channel identifier for an incoming data flit; storing the virtual channel identifier in a data pipeline and a bad data indicator (BDI) pipeline; receiving, from the cross-chip link, the incoming data flit into the data pipeline; moving, based on the virtual channel identifier in the data pipeline, the data flit from the data pipeline into an entry in a virtual channel queue corresponding to the virtual channel identifier; receiving, from the cross-chip link, a BDI for the data flit into the BDI pipeline; and moving, based on the virtual channel identifier in the BDI pipeline, the BDI for the data flit from the BDI pipeline into an entry in a BDI array corresponding to the entry in the virtual channel queue storing the data flit.

公开(公告)号：US20190087355A1

公开(公告)日：2019-03-21

申请号：US16130858

申请日：2018-09-13

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Fabrice ROMAIN

IPC: G06F12/14 ,  G06F11/00

CPC classification number: G06F12/1458 ,  G06F11/006 ,  G06F12/1408 ,  G06F2201/805 ,  G06F2212/1052 ,  G06F2221/2141

Abstract: The present disclosure concerns a memory access control system comprising: a processing device capable of operating in a plurality of operating modes, and of accessing a memory using a plurality of address aliases; and a verification circuit configured: to receive, in relation with a first read operation of a first memory location in the memory, an indication of a first of said plurality of address aliases associated with the first read operation; to verify that a current operating mode of the processing device permits the processing device to access the memory using the first address alias; to receive, during the first read operation, a first marker stored at the first memory location; and to verify, based on the first marker and on the first address alias, that the processing device is permitted to access the first memory location.

公开(公告)号：US20190087287A1

公开(公告)日：2019-03-21

申请号：US16141269

申请日：2018-09-25

Applicant: Microsoft Technology Licensing, LLC

Inventor： James W. MICKENS ,  Amar PHANISHAYEE ,  Vijaychidambaram VELAYUDHAN PILLAI

IPC: G06F11/14 ,  G06F3/06

CPC classification number: G06F11/1471 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0689 ,  G06F11/14 ,  G06F11/1469 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2201/84

Abstract: This document relates to data storage techniques. One example can buffer write commands and cause the write commands to be committed to storage in flush epoch order. Another example can maintain a persistent log of write commands that are arranged in the persistent log in flush epoch order. Both examples may provide a prefix consistent state in the event of a crash.

公开(公告)号：US20190065324A1

公开(公告)日：2019-02-28

申请号：US15691823

申请日：2017-08-31

Applicant: International Business Machines Corporation

Inventor： Gaurav Mehrotra ,  Nishant Sinha ,  Pratik P. Paingankar

IPC: G06F11/14 ,  G06F17/30

CPC classification number: G06F11/1469 ,  G06F11/1456 ,  G06F11/1458 ,  G06F11/2094 ,  G06F16/2282 ,  G06F16/24578 ,  G06F2201/80 ,  G06F2201/805 ,  G06F2201/82

Abstract: A means for assigning database objects to a backup storage group proceeds by collecting information related to a plurality of backup devices. The information collected includes speed of recovery, time to backup, and a recovery rank for each device. A backup pool is defined, using a database configuration parameter, to contain one or more of the plurality of backup devices. A determination is made to store a backup of a data object in a first device of the plurality of backup devices based on the collected information and a priority rank associated with the data object.

公开(公告)号：US20190065175A1

公开(公告)日：2019-02-28

申请号：US16058705

申请日：2018-08-08

Applicant: Onkyo Corporation

Inventor： Kazunari ITO

IPC: G06F8/654 ,  G06F11/14

CPC classification number: G06F8/654 ,  G06F8/65 ,  G06F11/142 ,  G06F2201/805

Abstract: An electronic device includes a volatile memory; a non-volatile memory which is for storing firmware; and a circuit, wherein the firmware includes firmware body and loader which is for rewriting the non-volatile memory, and the circuit, judges whether the firmware is being rewritten or not based on a first mark when activating, judges whether the loader is being rewritten or not based on a second mark when it judges that the firmware is being rewritten, copies the loader which is copied to the other position of the non-volatile memory to the volatile memory when it judges that the loader is being rewritten, and executes the loader which is copied to the volatile memory and rewrites the firmware which is stored in the non-volatile memory.

公开(公告)号：US20190042346A1

公开(公告)日：2019-02-07

申请号：US15665454

申请日：2017-08-01

Applicant: International Business Machines Corporation

Inventor： Volker Boenisch ,  Reinhard T. Buendgen ,  Franziska Geisert ,  Michael Holzheu ,  Jakob C. Lang ,  Angel Nunez Mencias

IPC: G06F11/07 ,  G06F11/14 ,  G06F11/20 ,  G06F1/30

CPC classification number: G06F11/0778 ,  G06F1/30 ,  G06F11/0724 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1417 ,  G06F11/1441 ,  G06F11/2015 ,  G06F2201/805 ,  G06F2201/815

Abstract: Methods and systems for executing dumping of main memory content and CPU states and for an adaptive boot. The methods and the systems provide a configuration list of the computer system comprising a pre-defined set of dedicated resources for the dumping, provide threshold values for a pre-defined set of minimum resources for executing a reboot of the computer system, assign the pre-defined set of the dedicated resources for executing the dumping, start the dumping, release ones of the dedicated resources after content of the ones of the dedicated resources has been dumped, start a reboot process of the computer system in response to determining that the ones of the dedicated resources exceeds the threshold values for the pre-defined set of the minimum resources for executing the reboot process, and continue to release others of the dedicated resources to the reboot process until the dumping is completed.

公开(公告)号：US20190034299A1

公开(公告)日：2019-01-31

申请号：US15664001

申请日：2017-07-31

Applicant: International Business Machines Corporation

Inventor： Colin R. Devilbiss ,  Charles S. Graham ,  James B. Cunningham

IPC: G06F11/20

CPC classification number: G06F11/2033 ,  G06F11/1484 ,  G06F2201/805

Abstract: The present invention provides computer implemented method, system, and computer program product of switching servers without interrupting a client command-response queue. In an embodiment, the present invention includes selecting standby computer server systems, connecting a CRQ of a client computer system to a previous active computer server system and to the selected standby computer server systems, transmitting setup commands to the selected standby computer server systems, communicating data with the previous active computer server system via at least one sub-CRQ, communicating management commands with the previous active computer server system and the selected standby computer server systems via the CRQ, receiving a notification that a switchover has occurred, redirecting the CRQ to one of the selected standby computer server systems, in response to the redirecting, communicating data with a new active computer server system via at least one sub-CRQ, and sending new setup commands to the new computer server system.

公开(公告)号：US20190012241A1

公开(公告)日：2019-01-10

申请号：US16128741

申请日：2018-09-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Karl Gschwind ,  Valentina Salapura

IPC: G06F11/14 ,  G06F3/06 ,  G06F13/24 ,  G06F9/46

CPC classification number: G06F11/1474 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/466 ,  G06F11/1407 ,  G06F11/1438 ,  G06F11/1451 ,  G06F13/24 ,  G06F2201/805 ,  G06F2201/825 ,  G06F2201/84

Abstract: Autonomous recovery from a transient hardware failure by executing portions of a stream of program instructions as a transaction. A start of a transaction is created in a stream of executing program instructions. A snapshot of a system state information is saved when the transaction begins. When a predefined number of program instructions in the stream are executed, the transaction ends, and store data of the transaction is committed. A new transaction then begins. If a transient hardware failure occurs, the transaction is aborted without notifying the computer software application that initiated the stream of program instructions. The transaction is re-executed, based on the saved snapshot of the system state information.