公开(公告)号：US20140059334A1

公开(公告)日：2014-02-27

申请号：US14067212

申请日：2013-10-30

Applicant: Venkat Rajeev Indukuru ,  Daniel Owen ,  Alexander Erik Mericas ,  John Fred Spannaus

Inventor： Venkat Rajeev Indukuru ,  Daniel Owen ,  Alexander Erik Mericas ,  John Fred Spannaus

IPC: G06F9/38

CPC classification number: G06F11/3466 ,  G06F8/443 ,  G06F8/4442 ,  G06F9/3861 ,  G06F11/34 ,  G06F11/3471 ,  G06F11/3476 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular event generates large data logs, creates performance penalties, and makes code analysis more difficult. However, by identifying and tracking the worst offenders within a random sample of events without having to hash all events results in smaller memory requirements for the performance profiler, lower performance impact while profiling, and decreased complexity to analyze the program to identify major performance issues, which, in turn, enables better optimization of the program in shorter developer time.

Abstract translation: 处理器性能分析器能够用于识别由微处理器通过随机采样来执行的程序中导致性能问题的特定指令，以找到诸如高速缓存未命中或分支误预测的特定事件类型的最坏情况的违规者。 跟踪导致特定事件的所有指令会生成大量数据日志，创建性能损失，并使代码分析更加困难。 然而，通过识别和跟踪随机事件样本中的最坏罪犯，而不必对所有事件进行散列，从而导致性能分析器的较小内存需求，降低性能影响，同时分析并降低分析程序以识别主要性能问题的复杂性， 这反过来，可以在较短的开发人员时间内更好地优化程序。

公开(公告)号：US20130339610A1

公开(公告)日：2013-12-19

申请号：US13523686

申请日：2012-06-14

Applicant: Adam B. Collura ,  Brian R. Prasky

Inventor： Adam B. Collura ,  Brian R. Prasky

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F9/38 ,  G06F9/3824 ,  G06F11/34 ,  G06F11/3471 ,  G06F12/0802 ,  G06F2201/885

Abstract: Embodiments relate to tracking cache lines. An aspect of embodiments includes performing an operation by a processor. Another aspect of embodiments includes fetching a cache line based on the operation. Yet another aspect of embodiments includes storing in an instruction address register file at least one of (i) an operation identifier identifying the operation and (ii) a memory location identifier identifying a level of memory from which the cache line is populated.

Abstract translation: 实施例涉及跟踪高速缓存行。 实施例的一个方面包括执行处理器的操作。 实施例的另一方面包括基于该操作获取高速缓存行。 实施例的另一方面包括在指令地址寄存器文件中存储以下至少一个：（i）识别操作的操作标识符和（ii）识别高速缓存线从其填充的存储器级别的存储器位置标识符。

公开(公告)号：US20130332778A1

公开(公告)日：2013-12-12

申请号：US13491444

申请日：2012-06-07

Applicant: Lawrence Andrew Spracklen

Inventor： Lawrence Andrew Spracklen

IPC: G06F11/34

CPC classification number: G06F9/45533 ,  G06F9/4881 ,  G06F9/52 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3433 ,  G06F11/348 ,  G06F2201/81 ,  G06F2201/815 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2201/885

Abstract: The current application is directed to architected hardware support within computer processors for detecting and monitoring various types of potential performance imbalances with respect to simultaneously executing hardware threads in simultaneous multi-threading (“SMT”) processors and SMT-processor cores. The architected hardware support may include various types of performance-imbalance-monitoring registers that accumulate indications of performance imbalances and that can be used, by performance-monitoring software and by human analysts to detect performance-degrading conflicts between simultaneously executing hardware threads. Such conflicts can be ameliorated by changing the scheduling of virtual machines, tasks, and other computational entities, by redesigning and re-implementing all or portions of performance-limited and performance-degrading applications, by altering resource-allocation strategies, and by other means. In addition, performance imbalance detection and monitoring can be used to provide accurate, computational-throughput-based accounting in cloud-computing environments.

Abstract translation: 目前的应用针对计算机处理器内的架构硬件支持，用于检测和监测同时执行同时多线程（“SMT”）处理器和SMT处理器内核中的硬件线程的各种类型的潜在性能不平衡。 架构化的硬件支持可能包括各种类型的性能不平衡监控寄存器，累积性能不平衡的指示，并且可以通过性能监视软件和人类分析人员来检测同时执行硬件线程之间的性能降级冲突。 通过改变虚拟机，任务和其他计算实体的调度，可以通过重新设计和重新实施性能受限和性能降级的应用程序的全部或部分，通过改变资源分配策略和其他方式来改善这种冲突 。 此外，性能不平衡检测和监控可用于在云计算环境中提供准确的基于计算吞吐量的计费。

公开(公告)号：US20130318305A1

公开(公告)日：2013-11-28

申请号：US13954929

申请日：2013-07-30

Applicant: International Business Machines Corporation

Inventor： John Alan Bivens ,  Parijat Dube ,  Michael Mi Tsao ,  Li Zhang

IPC: G06F12/12 ,  G06F12/06

CPC classification number: G06F12/121 ,  G06F11/3409 ,  G06F11/3428 ,  G06F11/3447 ,  G06F11/3452 ,  G06F11/3471 ,  G06F12/0646 ,  G06F12/0802 ,  G06F2201/885 ,  G06F2212/601

Abstract: A method for configuring a large hybrid memory subsystem having a large cache size in a computing system where one or more performance metrics of the computing system are expressed as an explicit function of configuration parameters of the memory subsystem and workload parameters of the memory subsystem. The computing system hosts applications that utilize the memory subsystem, and the performance metrics cover the use of the memory subsystem by the applications. A performance goal containing values for the performance metric is identified for the computing system. These values for the performance metrics are used in the explicit function of performance metrics, configuration parameters and workload parameters to calculate values for the configuration parameters that achieve the identified performance goal. The calculated values of the configuration parameters are implemented in the memory subsystem.

Abstract translation: 一种用于在计算系统中配置具有大缓存大小的大型混合存储器子系统的方法，其中计算系统的一个或多个性能度量被表示为存储器子系统的配置参数和存储器子系统的工作负载参数的明确函数。 计算系统托管利用内存子系统的应用程序，性能指标涵盖应用程序对内存子系统的使用。 为计算系统识别包含性能指标值的性能目标。 性能指标的这些值用于性能度量，配置参数和工作负载参数的显式功能，以计算实现已识别性能目标的配置参数的值。 配置参数的计算值在存储器子系统中实现。

公开(公告)号：US08521499B1

公开(公告)日：2013-08-27

申请号：US13038152

申请日：2011-03-01

Applicant: Karl Van Rompaey ,  Andreas Wieferink

Inventor： Karl Van Rompaey ,  Andreas Wieferink

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F11/3457 ,  G06F2201/885 ,  G06F2217/40

Abstract: Systems and methods for run-time switching for simulation with dynamic run-time accuracy adjustment. In one embodiment, a computer implemented method performs a simulation of a computer instruction executing on a simulated hardware design by a first simulation model, wherein the first simulation model provides first timing information of the simulation. The first timing information is stored to a computer usable media. A pending subsequent simulation of the instruction is detected. Responsive to the presence of the first timing information in the computer usable media, the computer instruction is simulated by a second simulation model, wherein the second simulation model provides less accurate second timing information of the simulation than the first simulation model. The simulation run time information is updated for the subsequent simulation with the first timing information.

Abstract translation: 用于运行时切换的系统和方法，用于动态运行时精度调整。 在一个实施例中，计算机实现的方法通过第一仿真模型执行对模拟硬件设计执行的计算机指令的模拟，其中第一模拟模型提供模拟的第一定时信息。 第一定时信息被存储到计算机可用媒体。 检测到指令的待决后续仿真。 响应于计算机可用介质中存在第一定时信息，通过第二仿真模型来模拟计算机指令，其中第二仿真模型提供比第一仿真模型更少的准确的模拟第二定时信息。 模拟运行时间信息被更新为随后的模拟与第一定时信息。

公开(公告)号：US20130138889A1

公开(公告)日：2013-05-30

申请号：US13306996

申请日：2011-11-30

Applicant: Gregory Chockler ,  Guy Laden ,  Ýmir Vigfússon

Inventor： Gregory Chockler ,  Guy Laden ,  Ýmir Vigfússon

IPC: G06F12/08

CPC classification number: G06F12/0866 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3466 ,  G06F2201/885

Abstract: Systems and methods for cache optimization, the method comprising monitoring cache access rate for one or more cache tenants in a computing environment, wherein a first cache tenant is allocated a first cache having a first cache size which may be adjusted; determining a cache profile for at least the first cache over one or more time intervals according to data collected during the monitoring, analyzing the cache profile for the first cache to determine an expected cache usage model for the first cache; and analyzing the cache usage model and factors related to cache efficiency for the one or more cache tenants to dictate one or more constraints that define boundaries for the first cache size.

Abstract translation: 用于高速缓存优化的系统和方法，所述方法包括监视计算环境中的一个或多个高速缓存租户的高速缓存访​​问速率，其中为第一高速缓存租户分配具有可调整的第一高速缓存大小的第一高速缓存; 根据在监视期间收集的数据，通过一个或多个时间间隔确定至少第一高速缓存的高速缓存简档，分析第一高速缓存的高速缓存配置文件，以确定第一高速缓存的预期高速缓存使用模型; 以及分析所述高速缓存使用模型和与所述一个或多个高速缓存租户相关的因素，以规定限定所述第一高速缓存大小的边界的一个或多个约束。

公开(公告)号：US08453146B2

公开(公告)日：2013-05-28

申请号：US12645609

申请日：2009-12-23

Applicant: Christopher J. Cormack ,  Nathaniel Duca

Inventor： Christopher J. Cormack ,  Nathaniel Duca

IPC: G06F9/455

CPC classification number: G06F11/3409 ,  G06F11/3442 ,  G06F11/3466 ,  G06F11/348 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2201/885

Abstract: A technique includes providing data indicative of a counted value acquired by a hardware counter of a processing core during a time segment in which a plurality of tasks are active on the core and, in a processor-based machine, determining a likelihood that the counted value is attributable to a given task of the tasks during the time segment and attributing a portion of the counted value to the given task based at least in part on the determined likelihood.

Abstract translation: 一种技术包括提供表示由处理核心的硬件计数器获取的计数值的数据，其中多个任务在核心上处于活动状态的时间段内，并且在基于处理器的机器中，确定计数值 归因于在时间段期间的任务的给定任务，并且至少部分地基于所确定的可能性将所计数的值的一部分归因于给定任务。

公开(公告)号：US08453121B2

公开(公告)日：2013-05-28

申请号：US12132024

申请日：2008-06-03

Applicant: Alexis Birkill ,  George Meldrum Blue ,  Philip Graham Willoughby

Inventor： Alexis Birkill ,  George Meldrum Blue ,  Philip Graham Willoughby

IPC: G06F9/44

CPC classification number: G06F11/3476 ,  G06F11/3409 ,  G06F2201/86 ,  G06F2201/885

Abstract: A method and system for the management of tracing data of interest in a data processing system comprises identifying the location and length of one or more such units of interest as each unit is stored in main memory during execution of the program and recording a logical assignment of each unit of interest to a slot in a wrap around trace buffer. Copying of the units of interest to the trace buffer is deferred unless one or more predefined events occur. Such events may include an attempt to overwrite the data which has been logically assigned or a request for information stored in the trace buffer. The recorded assignments are discarded whenever it is calculated that the capacity of the trace buffer would be exceeded resulting in the corresponding units never needing to be copied to the trace buffer.

Abstract translation: 一种用于管理数据处理系统中感兴趣的跟踪数据的方法和系统包括：在执行程序期间，每个单元存储在主存储器中，识别一个或多个这样的感兴趣单元的位置和长度，并记录 每个单位感兴趣的一个插槽中绕着缓冲区。 除非发生一个或多个预定义的事件，否则将追踪跟踪缓冲区的单位复制。 这种事件可能包括尝试覆盖逻辑分配的数据或存储在跟踪缓冲器中的信息请求。 如果计算出跟踪缓冲区的容量将被超出，则记录的分配将被丢弃，导致相应的单元不需要复制到跟踪缓冲区。

公开(公告)号：US20130091319A1

公开(公告)日：2013-04-11

申请号：US13253126

申请日：2011-10-05

Applicant: Byungcheol Cho

Inventor： Byungcheol Cho

IPC: G06F12/02 ,  G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0888 ,  G06F11/1441 ,  G06F11/3433 ,  G06F11/3485 ,  G06F2201/885

Abstract: Embodiments of the present invention provide an adaptive cache system and an adaptive cache system for a hybrid storage system. Specifically, in a typical embodiment, an input/out (I/O) traffic analysis component is provided for monitoring data traffic and providing a traffic analysis based thereon. An adaptive cache algorithm component is coupled to the I/O traffic analysis component for applying a set of algorithms to determine a storage schema for handling the data traffic. Further, an adaptive cache policy component is coupled to the adaptive cache algorithm component.

Abstract translation: 本发明的实施例提供了一种用于混合存储系统的自适应高速缓存系统和自适应高速缓存系统。 具体地说，在典型的实施例中，提供了一种输入/输出（I / O）业务分析组件，用于监视数据流量并提供基于此的流量分析。 自适应高速缓存算法组件耦合到I / O流量分析组件，以应用一组算法来确定用于处理数据业务的存储模式。 此外，自适应高速缓存策略组件耦合到自适应高速缓存算法组件。

公开(公告)号：US08365184B2

公开(公告)日：2013-01-29

申请号：US11848661

申请日：2007-08-31

Applicant: Stephen R Carter

Inventor： Stephen R Carter

IPC: G06F9/50 ,  G06F11/30

CPC classification number: G06F9/5027 ,  G06F11/3419 ,  G06F11/3433 ,  G06F11/3447 ,  G06F11/3495 ,  G06F2201/86 ,  G06F2201/885

Abstract: Techniques for multi-core resource utilization planning are provided. An agent is deployed on each core of a multi-core machine. The agents cooperate to perform one or more tests. The tests result in measurements for performance and thermal characteristics of each core and each communication fabric between the cores. The measurements are organized in a resource utilization map and the map is used to make decisions regarding core assignments for resources.