公开(公告)号：US20150348764A1

公开(公告)日：2015-12-03

申请号：US14288157

申请日：2014-05-27

Applicant: WD Media, LLC

Inventor： ALLEN J. BOUREZ ,  YEW MING CHIONG

IPC: H01J37/32

CPC classification number: H01J37/32899 ,  H01J37/32715 ,  H01L21/67103 ,  H01L21/67173 ,  H01L21/67712 ,  H01L21/68771 ,  H01L21/68785 ,  H01L21/68792

Abstract: Various embodiments provide a substrate carrier configured to rotatably carry at least one substrate through a plurality of processing stations. The substrate carrier includes an integrated heater for heating a first side of the substrate while the second side of the substrate undergoes one or more manufacturing processes at each of the plurality of processing stations, e.g., to promote the desired growth of HAMR media. This can result in the elimination of one or more processing stations, thereby realizing cost savings, decreased substrate processing time, as well as a reduced area within which a substrate processing system can be implemented.

Abstract translation: 各种实施例提供了一种被配置为可旋转地承载至少一个基板通过多个处理站的基板载体。 衬底载体包括用于加热衬底的第一侧的集成加热器，而衬底的第二侧在多个处理站中的每一个处经历一个或多个制造工艺，例如以促进HAMR介质的期望生长。 这可以导致一个或多个处理站的消除，从而实现成本节约，减少的基板处理时间，以及可以实现基板处理系统的减小的面积。

公开(公告)号：US09177806B2

公开(公告)日：2015-11-03

申请号：US13017828

申请日：2011-01-31

Applicant: Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01J37/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract translation: 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

公开(公告)号：US20150303065A1

公开(公告)日：2015-10-22

申请号：US14257744

申请日：2014-04-21

Applicant: Lam Research Corporation

Inventor： Bryan L. Buckalew ,  Mark L. Rea

IPC: H01L21/3065 ,  C25D5/48 ,  C25D7/12 ,  H01L21/027 ,  H01L21/02

CPC classification number: H01L21/02068 ,  C23C18/1605 ,  C23C18/1803 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D7/123 ,  G03F7/427 ,  H01J37/32357 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/0206 ,  H01L21/0273 ,  H01L21/6723 ,  H01L21/76862 ,  H01L21/76873 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/0381 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1161 ,  H01L2224/1181 ,  H01L2224/13018 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/014

Abstract: Certain embodiments herein relate to methods and apparatus for processing a partially fabricated semiconductor substrate in a remote plasma environment. The methods may be performed in the context of wafer level packaging (WLP) processes. The methods may include exposing the substrate to a reducing plasma to remove photoresist scum and/or oxidation from an underlying seed layer. In some cases, photoresist scum is removed through a series of plasma treatments involving exposure to an oxygen-containing plasma followed by exposure to a reducing plasma. In some embodiments, an oxygen-containing plasma is further used to strip photoresist from a substrate surface after electroplating. This plasma strip may be followed by a plasma treatment involving exposure to a reducing plasma. The plasma treatments herein may involve exposure to a remote plasma within a plasma treatment module of a multi-tool electroplating apparatus.

Abstract translation: 本文中的某些实施例涉及用于在远程等离子体环境中处理部分制造的半导体衬底的方法和装置。 这些方法可以在晶片级封装（WLP）工艺的上下文中进行。 所述方法可以包括将衬底暴露于还原等离子体以从底层种子层去除光致抗蚀剂浮渣和/或氧化。 在一些情况下，通过一系列等离子体处理除去光致抗蚀剂浮渣，包括暴露于含氧等离子体，然后暴露于还原等离子体。 在一些实施例中，进一步使用含氧等离子体在电镀之后从基板表面剥离光致抗蚀剂。 该等离子体条之后可以进行涉及暴露于还原等离子体的等离子体处理。 这里的等离子体处理可能涉及暴露于多工具电镀设备的等离子体处理模块内的远程等离子体。

公开(公告)号：US20150255257A1

公开(公告)日：2015-09-10

申请号：US14440487

申请日：2013-10-25

Applicant: TOKYO ELECTRON LIMITED

Inventor： Atsushi Kawabe ,  Sensho Kobayashi

IPC: H01J37/32

CPC classification number: H01J37/32724 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32522 ,  H01J37/32733 ,  H01J37/32816 ,  H01J37/32834 ,  H01J37/32899 ,  H01J2237/002 ,  H01J2237/334 ,  H01L21/67109 ,  H01L21/67201

Abstract: An objective of the present invention is to simplify a configuration of a processing chamber for cooling a substrate in a substrate processing device. In a plasma processing device (10) whereby a plasma process is carried out upon a wafer (W), the wafer (W) which is plasma processed is conveyed into a load-lock chamber (13), and gas is discharged from a gas discharge member (25) upon the surface of the wafer (W), cooling the wafer (W). The gas discharge member (25) comprises a structure wherein a plurality of gas discharge nozzles (35) are formed in one flat plate face of a flat plate member (31). The gas discharge nozzles (35) comprise cylindrical eddy generating chambers (41), and nozzle holes (42) which are opened in bottom walls (52) of the eddy generating chambers (41) and discharge the gas. The flat plate face of the wafer (W) and the flat plate face wherein the gas discharge nozzles (35) are formed in the flat plate member (31) are positioned in parallel at a prescribed gap. A purge gas is discharged from the nozzle holes (42) toward the wafer (W), and a flow of an eddy is made to arise in the discharged purge gas, thereby cooling the wafer (W), and simultaneously switching the interior of the load-lock chamber (13) from a vacuum environment to an atmospheric pressure environment.

Abstract translation: 本发明的目的是简化用于冷却衬底处理装置中的衬底的处理室的构造。 在等离子体处理装置（10）中，通过对晶片（W）进行等离子体处理，将等离子体处理的晶片（W）输送到负载锁定室（13），从气体中排出气体 放电构件（25）在晶片（W）的表面上，冷却晶片（W）。 气体排出构件（25）包括在平板构件（31）的一个平板面上形成有多个排气喷嘴（35）的结构。 排气喷嘴（35）包括圆筒形涡流发生室（41）和在涡流发生室（41）的底壁（52）中打开并排出气体的喷嘴孔。 晶片（W）的平板面和平板面，其中在平板构件（31）中形成气体排出喷嘴（35）的平板面以规定的间隙平行放置。 吹扫气体从喷嘴孔（42）朝向晶片（W）排出，并且在排出的净化气体中产生涡流，从而冷却晶片（W），同时切换 负载锁定室（13）从真空环境到大气压力环境。

公开(公告)号：US09119283B2

公开(公告)日：2015-08-25

申请号：US13901509

申请日：2013-05-23

Applicant: Lam Research Corporation

Inventor： Luc Albarede

IPC: H01J7/24 ,  H05H1/46 ,  H01J37/32

CPC classification number: H05H1/46 ,  H01J37/32183 ,  H01J37/32899 ,  H05H2001/4682

Abstract: Systems and methods for performing chamber matching are described. One of the methods for performing chamber matching includes executing a first test within a first plasma chamber to measure a variable and executing a second test within a second plasma chamber to measure the variable. The first and second tests are executed based on one recipe. The method further includes determining a first relationship between the variable measured with the first test and power provided during the first test, determining a second relationship between the variable measured with the second test and power provided during the second test, and identifying power adjustment to apply to the second plasma chamber during a subsequent processing operation based on the first and second relationships. The power adjustment causes the second plasma chamber to perform the processing operation in a processing condition determined using the first plasma chamber.

Abstract translation: 描述了用于执行室匹配的系统和方法。 执行室匹配的方法之一包括在第一等离子体室内执行第一测试以测量变量并在第二等离子体室内执行第二测试以测量该变量。 第一个和第二个测试是基于一个配方执行的。 该方法还包括确定用第一测试测量的变量与在第一测试期间提供的功率之间的第一关系，确定用第二测试测量的变量与第二测试期间提供的功率之间的第二关系，以及识别要应用的功率调整 在后续处理操作期间基于第一和第二关系到第二等离子体室。 功率调整使得第二等离子体室在使用第一等离子体室确定的处理条件下进行处理操作。

公开(公告)号：US09039873B2

公开(公告)日：2015-05-26

申请号：US13919067

申请日：2013-06-17

Applicant: CANON ANELVA CORPORATION

Inventor： Koji Tsunekawa

IPC: C23C14/56 ,  C23C14/34 ,  C23C14/58 ,  C23C14/14 ,  H01L43/08 ,  H01L43/12 ,  H01L21/67 ,  C23C28/00

CPC classification number: C23C14/14 ,  C23C14/067 ,  C23C14/081 ,  C23C14/34 ,  C23C14/3407 ,  C23C14/345 ,  C23C14/3464 ,  C23C14/505 ,  C23C14/568 ,  C23C14/5806 ,  C23C14/5853 ,  C23C28/321 ,  C23C28/322 ,  C23C28/34 ,  C23C28/345 ,  H01F41/18 ,  H01J37/32899 ,  H01J37/3405 ,  H01J37/3411 ,  H01J37/3417 ,  H01L21/67207 ,  H01L43/08 ,  H01L43/12

Abstract: The present invention provides a manufacturing apparatus which can realize so-called sequential substrate transfer and can improve throughput, even when one multi-layered thin film includes plural layers of the same film type. A manufacturing apparatus according to an embodiment of the present invention includes a transfer chamber, three sputtering deposition chambers each including one sputtering cathode, two sputtering deposition chambers each including two or more sputtering cathodes, and a process chamber for performing a process other than sputtering, and the three sputtering deposition chambers, the two sputtering deposition chambers, and the process chamber are arranged around the transfer chamber so that each is able to perform delivery and receipt of the substrate with the transfer chamber.

Abstract translation: 本发明提供一种制造装置，即使在一层多层薄膜包含多层相同膜型的情况下，也能够实现所谓的顺序基板转印，并能提高生产量。 根据本发明的实施例的制造装置包括转移室，每个包括一个溅射阴极的三个溅射沉积室，每个包括两个或更多个溅射阴极的两个溅射沉积室，以及用于进行溅射以外的处理的处理室， 并且三个溅射沉积室，两个溅射沉积室和处理室布置在传送室周围，使得每个溅射沉积室能够使用传送室执行传送和接收基板。

公开(公告)号：US20150096685A1

公开(公告)日：2015-04-09

申请号：US14183554

申请日：2014-02-19

Applicant: Hitachi High-Technologies Corporation

Inventor： Kohei Sato ,  Akitaka Makino ,  Hiromichi Kawasaki

IPC: H01J37/32

CPC classification number: H01J37/32733 ,  H01J37/32724 ,  H01J37/32899 ,  H01L21/67184 ,  H01L21/67196 ,  H01L21/67201

Abstract: A plasma processing apparatus includes processing units, each of which subjects a sample to processing inside a processing chamber in a vacuum vessel, vacuum transfer chambers which are coupled to the processing units and each have an interior where a sample is transferred under reduced pressure, an intermediate chamber which has, in an interior, a space where a transferred sample is housed, a buffer chamber which is capable of housing a sample arranged in an interior of the vessel, a mounting table which is arranged in the buffer chamber and is adjusted to a prescribed temperature and on which a sample is placed, an opening through which a sample is taken in or out, and a lid member which opens or hermetically closes the opening, and a sample is transferred between the processing unit and a lock chamber via the buffer chamber.

Abstract translation: 等离子体处理装置包括处理单元，每个处理单元使样品在真空容器内的处理室内进行处理，耦合到处理单元并且各自具有在减压下转移样品的内部的真空转移室， 中间室在内部具有容纳转移样品的空间，能够容纳布置在容器内部的样品的缓冲室，安装台，其布置在缓冲室中并被调节到 规定的温度，其上放置样品，将样品取入或取出的开口，以及打开或气密地关闭开口的盖构件，并且样品经由所述处理单元和锁定室之间经由 缓冲室。

公开(公告)号：US20150083331A1

公开(公告)日：2015-03-26

申请号：US14556008

申请日：2014-11-28

Applicant: Yong Hyun LEE ,  Myung Jin LEE ,  An Ki CHA

Inventor： Yong Hyun LEE ,  Myung Jin LEE ,  An Ki CHA

IPC: H01L21/677 ,  H01L21/306 ,  H01J37/32

CPC classification number: H01L21/67739 ,  H01J37/32458 ,  H01J37/32715 ,  H01J37/32899 ,  H01L21/306 ,  H01L21/67742 ,  H01L21/67745

Abstract: Disclosed herein is a semiconductor manufacturing apparatus including a transfer chamber provided with a substrate moving device to move substrates, a load lock chamber to align the substrates and to load and unload the substrates into and out of the transfer chamber, and at least one process chamber to process the substrates transferred from the transfer chambers. Each of the at least one process chamber includes a chamber provided with a substrate entrance formed on a side surface thereof, a substrate support provided within the chamber such that at least two substrates are disposed on the substrate support, and at least one divider provided within the chamber to align the at least two substrates.

Abstract translation: 本文公开了一种半导体制造装置，包括：传送室，设置有用于移动基板的基板移动装置;负载锁定室，其对准基板并将基板装载和卸载到输送室中;以及至少一个处理室 以处理从转印室转印的基材。 所述至少一个处理室中的每一个包括设置有形成在其侧表面上的基板入口的室，设置在所述室内的基板支撑件，使得至少两个基板设置在所述基板支撑件上， 所述腔室对准所述至少两个基板。

公开(公告)号：US20150059647A1

公开(公告)日：2015-03-05

申请号：US14391959

申请日：2013-04-12

Applicant: IIa Technologies pte. Ltd.

Inventor： Devi Shanker Misra

IPC: C30B25/10 ,  C30B29/04 ,  C30B25/20 ,  C30B25/12 ,  C30B25/14

CPC classification number: C30B25/105 ,  C23C16/27 ,  C23C16/4402 ,  C23C16/4585 ,  C23C16/54 ,  C30B25/025 ,  C30B25/12 ,  C30B25/14 ,  C30B25/20 ,  C30B29/04 ,  H01J37/32192 ,  H01J37/3244 ,  H01J37/32724 ,  H01J37/32899

Abstract: An apparatus for growing diamonds, the apparatus comprising: one or more chambers, each chamber is in fluid connection with one or more other chambers, each chamber comprising one or more substrate stage assembly within the chamber to support a substrate stage having a plurality of diamond seeds disposed thereon.

Abstract translation: 一种用于生长钻石的装置，所述装置包括：一个或多个室，每个室与一个或多个其它室流体连接，每个室包括在所述室内的一个或多个衬底台组件，以支撑具有多个金刚石的衬底台 放置在其上的种子。

公开(公告)号：US20150056385A1

公开(公告)日：2015-02-26

申请号：US14464684

申请日：2014-08-20

Applicant: Tokyo Electron Limited

Inventor： Tadahiro ISHIZAKA ,  Kenji SUZUKI

IPC: H05K3/10 ,  H05K3/00

CPC classification number: H01L23/00 ,  C23C14/165 ,  C23C14/358 ,  H01J37/32899 ,  H01J37/34 ,  H01J37/3429 ,  H01L21/2855 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a Cu wiring structure forming method, a barrier film serving as a Cu diffusion barrier is formed at least on a surface of a recess in a first insulating film formed on a substrate, and the recess is filled with an Al-containing Cu film. A Cu wiring is formed from the Al-containing Cu film, and a cap layer including a Ru film is formed on the Cu wiring. Further, an interface layer containing a Ru—Al alloy is formed at an interface between the Cu wiring and the cap layer by heat generated in forming the cap layer or by a heat treatment performed after forming the cap layer. A second insulating film is formed on the cap layer.

Abstract translation: 在Cu布线结构形成方法中，至少在形成在基板上的第一绝缘膜的凹部的表面上形成用作Cu扩散阻挡层的阻挡膜，并且用含Al的Cu膜填充凹部。 由含Al的Cu膜形成Cu布线，在Cu布线上形成包含Ru膜的覆盖层。 此外，通过在形成盖层时产生的热或通过在形成盖层之后进行的热处理，在Cu布线和盖层之间的界面处形成含有Ru-Al合金的界面层。 在盖层上形成第二绝缘膜。