公开(公告)号：US11830802B2

公开(公告)日：2023-11-28

申请号：US17711890

申请日：2022-04-01

Applicant: Samsung Display Co., Ltd.

Inventor： Myongsoo Oh

IPC: H01L23/498 ,  G02F1/1345 ,  H10K59/88 ,  H10K59/131 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00 ,  H01L27/12 ,  H10K50/844 ,  H10K59/123 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: H01L23/49838 ,  G02F1/13452 ,  H01L23/49811 ,  H01L24/32 ,  H01L24/83 ,  H01L25/18 ,  H01L25/50 ,  H01L27/124 ,  H10K59/131 ,  H10K59/88 ,  G02F1/1368 ,  G02F1/136286 ,  H01L2224/32145 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15192 ,  H10K50/844 ,  H10K59/123

Abstract: A display device includes: a substrate; a pixel connected to a gate line and a data line on the substrate; a connection unit connected to one of the gate line and the data line of the substrate; and a driving integrated circuit mounted on the connection unit. The connection unit includes an output lead line, an auxiliary lead line and a first pattern, and the output lead line, auxiliary lead line and first pattern are sequentially disposed along a first direction on an output portion of the connection unit, an end portion of the first pattern is disposed on a first side of the connection unit, at least a portion of the auxiliary lead line is disposed on an input portion of the connection unit.

公开(公告)号：US20230326894A1

公开(公告)日：2023-10-12

申请号：US18078170

申请日：2022-12-09

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Fei-Jain Wu ,  Sheng-Jen Wu ,  Hsueh-Shun Yeh

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/13 ,  H01L2224/05573 ,  H01L24/16 ,  H01L24/32 ,  H01L24/83 ,  H01L24/81 ,  H01L24/05 ,  H01L21/563 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/3011 ,  H01L2224/32225 ,  H01L2224/81201 ,  H01L2224/83201 ,  H01L2224/13007 ,  H01L2224/13019 ,  H01L2224/1319 ,  H01L2224/13541 ,  H01L2224/13553 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L24/73

Abstract: In a bonding process of a flip chip bonding method, a chip is bonded to contact pads of a substrate by composite bumps which each includes a raiser, a UBM layer and a bonding layer. Before the bonding process, the surface of the bonding layer facing toward the substrate is referred to as a surface to be bonded. During the bonding process, the surface to be bonded is boned to the contact pad and become a bonding surface on the contact pad. The bonding surface has an area greater than that of the surface to be bonded so as to reduce electrical impedance between the chip and the substrate.

公开(公告)号：US11776932B2

公开(公告)日：2023-10-03

申请号：US15514598

申请日：2015-09-21

Applicant: DANFOSS SILICON POWER GMBH

Inventor： Ronald Eisele ,  Holger Ulrich

IPC: B23K1/00 ,  H01L23/00 ,  H05K3/32 ,  B22F3/14

CPC classification number: H01L24/83 ,  B22F3/14 ,  B23K1/0016 ,  H01L24/32 ,  H01L24/75 ,  H05K3/32 ,  B22F2301/10 ,  B22F2301/255 ,  H01L24/29 ,  H01L2224/29139 ,  H01L2224/29294 ,  H01L2224/29295 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32225 ,  H01L2224/755 ,  H01L2224/7511 ,  H01L2224/7525 ,  H01L2224/75101 ,  H01L2224/75102 ,  H01L2224/75315 ,  H01L2224/83048 ,  H01L2224/83075 ,  H01L2224/8384 ,  H01L2224/83095 ,  H01L2224/83101 ,  H01L2224/83201 ,  H01L2224/83204 ,  H01L2224/83911 ,  H01L2224/83948 ,  H05K2203/0278 ,  H05K2203/1131 ,  H05K2203/1157 ,  H01L2224/29339 ,  H01L2924/00014 ,  H01L2224/29294 ,  H01L2924/00014 ,  H01L2224/29347 ,  H01L2924/01047 ,  H01L2224/755 ,  H01L2924/00012

Abstract: Process for producing an electronic subassembly by low-temperature pressure sintering, comprising the following steps: arranging an electronic component on a circuit carrier having a conductor track, connecting the electronic component to the circuit carrier by the low-temperature pressure sintering of a joining material which connects the electronic component to the circuit carrier, characterized in that, to avoid the oxidation of the electronic component or of the conductor track, the low-temperature pressure sintering is carried out in a low-oxygen atmosphere having a relative oxygen content of 0.005 to 0.3%.

公开(公告)号：US20230282611A1

公开(公告)日：2023-09-07

申请号：US18159272

申请日：2023-01-25

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroki TAKAHASHI ,  Tsunehiro NAKAJIMA ,  Takashi SAITO

IPC: H01L23/00 ,  H01L25/07 ,  H01L25/00

CPC classification number: H01L24/83 ,  H01L24/95 ,  H01L24/32 ,  H01L24/29 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/95053 ,  H01L2224/83054 ,  H01L2224/83201 ,  H01L2224/8384 ,  H01L2224/83815 ,  H01L2224/83948 ,  H01L2224/83455 ,  H01L2924/0132 ,  H01L2224/83463 ,  H01L2924/01005 ,  H01L2224/83439 ,  H01L2224/83395 ,  H01L2224/29139 ,  H01L2224/32225 ,  H01L2924/13055 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/13091 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/73263 ,  H01L2224/40225 ,  H01L2224/73265 ,  H01L2224/73221 ,  H01L24/48 ,  H01L2224/48225 ,  H01L2224/48106 ,  H01L24/45 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45124 ,  H01L24/37 ,  H01L2224/37147 ,  H01L2224/37655 ,  H01L2224/37638

Abstract: When a semiconductor unit is heated, a heater having a flat heating surface is used for performing heating in a state in which a lower surface of an insulated circuit board is placed on the heating surface. When the semiconductor unit is cooled, a cooler having a cooling surface including a pair of support portions is used for performing cooling in which a lower surface of a pair of outer regions of the insulated circuit board are respectively placed to be contact with the pair of support portions, and in which a central region between the pair of outer regions of the insulated circuit board is pressed downward so as to be downward convex.

公开(公告)号：US20230215851A1

公开(公告)日：2023-07-06

申请号：US17922139

申请日：2021-05-14

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhijun LV ,  Feng ZHANG ,  Wenqu LIU ,  Xiaoxin SONG ,  Zhao CUI ,  Liwen DONG ,  Detian MENG ,  Libo WANG ,  Dongfei HOU ,  Lizhen ZHANG

IPC: H01L25/16 ,  H01L27/12 ,  H01L33/00 ,  H01L23/00 ,  H01F7/20 ,  H01F7/06

CPC classification number: H01L25/167 ,  H01L27/124 ,  H01L33/0093 ,  H01L24/05 ,  H01L24/95 ,  H01F7/20 ,  H01F7/064 ,  H01L2224/05573 ,  H01L2224/06131 ,  H01L24/06 ,  H01L24/83 ,  H01L2224/2957 ,  H01L2224/29611 ,  H01L2224/29639 ,  H01L24/29 ,  H01L2224/83201 ,  H01L2224/95136 ,  H01L2224/95133

Abstract: A driving backplane, a transfer method for a light-emitting diode chip (21), and a display apparatus. The driving backplane comprises: a base substrate (10), a driving circuit, a plurality of electromagnetic structures (13), and a plurality of contact electrodes (12). The plurality of electromagnetic structures (13) in the driving backplane are symmetrically arranged relative to a first straight line (L1) and a second straight line (L2). A current signal can be applied to each electromagnetic structure (13) by means of the driving circuit. Stress generated by a transfer carrier plate (20) according to the magnetic force of each electromagnetic structure (13) moves the transfer carrier plate (20). When the transfer carrier plate (20) is stress balanced in each direction parallel to the surface of the transfer carrier plate (20), the light-emitting diode chip (21) is precisely aligned to corresponding contact electrodes (12).

公开(公告)号：US20230207322A1

公开(公告)日：2023-06-29

申请号：US18147180

申请日：2022-12-28

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain, JR.

IPC: H01L21/20 ,  H01L23/498 ,  H01L21/768 ,  H01L25/00 ,  H01L27/06 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L21/2007 ,  H01L23/49866 ,  H01L21/76898 ,  H01L25/50 ,  H01L28/26 ,  H01L27/0688 ,  H01L21/6835 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2221/68359 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/83053 ,  H01L2224/83201 ,  H01L2225/06541

Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

公开(公告)号：US20230163096A1

公开(公告)日：2023-05-25

申请号：US18152478

申请日：2023-01-10

Applicant: TORAY ENGINEERING CO., LTD.

Inventor： Katsumi TERADA ,  Kenji HAMAKAWA ,  Takashi HARE ,  Yasushi TAMURA ,  Kensuke TASHIMA

IPC: H01L23/00 ,  H05K13/04 ,  H05K13/08

CPC classification number: H01L24/75 ,  H05K13/04 ,  H05K13/0812 ,  H05K13/0815 ,  H01L24/83 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75252 ,  H01L2224/75745 ,  H01L2224/75824 ,  H01L2224/75804 ,  H01L2224/83201 ,  H01L2224/83132 ,  H01L2224/8313

Abstract: A mounting device comprises a substrate stage, a mounting head, an elevating unit, a recognition mechanism, and a control unit. The recognition mechanism acquires position information about a chip recognition mark and a substrate recognition mark using an imaging unit. The control unit calculates an amount of positional deviation between a chip component and a substrate from the position information about the chip recognition mark and the substrate recognition mark, and performs alignment by driving the mounting head and/or the substrate stage according to the amount of the positional deviation. The chip component and the substrate are brought closer with each other and the alignment is performed in a state in which the imaging unit simultaneously images the chip recognition mark and the substrate recognition mark within a depth of field, after which the chip component and the substrate are brought into close contact with each other.

公开(公告)号：US10020278B2

公开(公告)日：2018-07-10

申请号：US15217199

申请日：2016-07-22

Applicant: Infineon Technologies AG

Inventor： Niels Oeschler

IPC: H01L23/00

CPC classification number: H01L24/27 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/27848 ,  H01L2224/32225 ,  H01L2224/83201 ,  H01L2224/83801

Abstract: A semiconductor chip includes a semiconductor body having a bottom side and a top side opposite the bottom side, and passivation arranged on the top side. The semiconductor chip is positioned on the carrier by picking the semiconductor chip and placing the semiconductor chip on the carrier, and pressing the semiconductor chip onto the carrier by a pressing force in a pressing direction, such that the pressing force acts on the semiconductor chip only above one or more continuous chip metallization sections arranged on the top side. Each of the one or more continuous chip metallization sections includes an annularly closed edge section which has a minimum width of more than zero in each direction perpendicular to the pressing direction. The pressing force does not act on the semiconductor chip above any of the edge sections.

公开(公告)号：US10008432B2

公开(公告)日：2018-06-26

申请号：US15215800

申请日：2016-07-21

Applicant: Socionext Inc.

Inventor： Takumi Ihara ,  Nobutaka Shimizu ,  Masamitsu Ikumo

IPC: H01L23/34 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/552 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/552 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/14051 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29387 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83201 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/27 ,  H01L2924/00012

Abstract: A semiconductor device includes a substrate and a semiconductor element mounted on the top surface of the substrate. On the top surface of the substrate, one or more pads are disposed outside the mounted semiconductor element when seen in a plan view. Then, a protrusion is disposed on each of the pads. A heat sink is disposed above the semiconductor element and the protrusions, and then bonded to the substrate by an adhesive provided between the heat sink and the substrate. The adhesive is provided in such a manner as to be in contact with the protrusions on the substrate.

公开(公告)号：US09960146B1

公开(公告)日：2018-05-01

申请号：US15462906

申请日：2017-03-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/02 ,  H01L21/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/2731 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/92143 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor structure includes a first stacking interposer. The first stacking interposer includes a first interposer having a first surface and a second surface opposite thereto; a plurality of first conductive pillars penetrating through the first interposer from the first surface to the second surface; a plurality of first bumps disposed at a side of the first surface of the first interposer and electrically connected to the first conductive pillars; and a first redistribution layer disposed on the second surface of the first interposer. The first surface has a clearance region where is free of the first bumps. A first chip is disposed over the first redistribution layer. The first chip is aligned with the clearance region of the first surface of the first interposer in a direction perpendicular to the first surface. A plurality of second bumps interconnecting the first redistribution layer with the first chip.