公开(公告)号：US07485411B2

公开(公告)日：2009-02-03

申请号：US11700864

申请日：2007-02-01

Applicant: Hyung Mi Jung ,  Yul Kyo Chung ,  Hyung Dong Kang

Inventor： Hyung Mi Jung ,  Yul Kyo Chung ,  Hyung Dong Kang

IPC: G03C5/00

CPC classification number: H05K1/162 ,  H05K3/16 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763

Abstract: In a method for manufacturing a printed circuit board with a thin film capacitor embedded therein, a conductive metal is sputtered via a first mask to form a lower electrode. A dielectric material is sputtered via a second mask to form a dielectric layer. The conductive metal is sputtered via a third mask to form an upper electrode. An insulating layer is stacked on a stack body with the upper electrode formed therein and via holes are perforated from a top surface of the insulating layer to a top surface of the lower electrode and from the top surface of the insulating layer to a top surface of the upper electrode formed on the substrate. Also, the stack body with the via holes formed therein is electrolytically and electrolessly plated.

Abstract translation: 在其中嵌入有薄膜电容器的印刷电路板的制造方法中，通过第一掩模溅射导电金属以形成下电极。 通过第二掩模溅射介电材料以形成电介质层。 通过第三掩模溅射导电金属以形成上电极。 绝缘层堆积在堆叠体上，上电极形成在其中，并且通孔从绝缘层的顶表面穿孔到下电极的顶表面，并从绝缘层的顶表面到 上电极形成在基板上。 此外，其中形成有通孔的堆叠体是电解和无电镀的。

公开(公告)号：US07470865B2

公开(公告)日：2008-12-30

申请号：US11429103

申请日：2006-05-08

Applicant: Takashi Fushie ,  Takeshi Kagatsume ,  Shigekazu Matsui

Inventor： Takashi Fushie ,  Takeshi Kagatsume ,  Shigekazu Matsui

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/426 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/388 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49165 ,  Y10T428/24926 ,  H01L2924/00

Abstract: A multilayer printed wiring board which permits the formation of fine wiring patterns, thereby increasing the density of wiring patterns. Using photosensitive glass having a coefficient of thermal expansion close to that of a copper film as a core substrate, a through hole is formed in the photosensitive glass by photolithography, a sputtering silicon oxide layer and a sputtering silicon nitride layer are formed to prevent leak of alkali metal ions from the photosensitive glass, a sputtering chromium layer, a sputtering chromium-copper layer and a sputtering copper layer are formed to enhance the adhesion strength between the copper film and the sputtering silicon oxide layer, and a copper film of 1 to 20 μm thick is formed. With resin filled into the interior of the through hole, a wiring layer is patterned by etching, an insulating layer is formed, and the surface is covered with a surface treatment layer and a cover coat.

Abstract translation: 允许形成精细布线图案的多层印刷布线板，从而增加布线图案的密度。 使用具有与铜膜接近的热膨胀系数的感光性玻璃作为芯基板，通过光刻在感光性玻璃中形成通孔，形成溅射氧化硅层和溅射氮化硅层，以防止泄漏 形成来自感光玻璃的碱金属离子，溅射铬层，溅射铬 - 铜层和溅射铜层，以提高铜膜和溅射氧化硅层之间的粘合强度，并使铜膜为1〜20 形成了厚厚的妈妈。 当树脂填充到通孔的内部时，通过蚀刻对布线层进行图案化，形成绝缘层，并且表面被表面处理层和覆盖层覆盖。

公开(公告)号：US20080310073A1

公开(公告)日：2008-12-18

申请号：US11912559

申请日：2006-04-28

Applicant: Akihiro Kanno ,  Akiko Sugioka ,  Naohiko Abe ,  Hirotake Nakashima

Inventor： Akihiro Kanno ,  Akiko Sugioka ,  Naohiko Abe ,  Hirotake Nakashima

IPC: H01G4/018 ,  B29C71/02

CPC classification number: H05K1/162 ,  C04B35/4682 ,  C04B35/47 ,  C04B35/624 ,  C04B2235/3213 ,  C04B2235/3215 ,  C04B2235/658 ,  C04B2235/661 ,  C23C18/06 ,  C23C18/1216 ,  C23C18/1241 ,  C23C18/1254 ,  C23C18/1275 ,  C23C18/1279 ,  C23C18/1283 ,  H01G4/1209 ,  H01G4/33 ,  H01G13/00 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09509

Abstract: The present invention has an object to provide a method for forming an oxide dielectric layer, which dielectric layer is formed by applying the sol-gel method, and is hardly damaged by an etching solution and excellent in dielectric characteristics such as a large electric capacitance. To achieve the object, the forming method of an oxide dielectric layer by applying a sol-gel method characterized by being provided with the following processes (a) to (c) is employed. Process (a): A solution preparing process of preparing a sol-gel solution for manufacturing an aiming oxide dielectric layer. Process (b): A coating process wherein stages of the sol-gel solution coating on the surface of a metal substrate followed by drying in an oxygen-containing atmosphere followed by pyrolysis in an oxygen-containing atmosphere sequentially is made one unit step; the one unit step is repeated twice or more times; and a pre-baking stage at 550-deg.C to 1000-deg.C in an inert gas-substituted atmosphere or the like is provided optionally between the one unit step and the next one unit step to control the film thickness. Process (c): A baking process of finally subjecting the coated metal substrate to a baking process at 550-deg.C to 1000-deg.C in an inert gas-substituted atmosphere or the like to finish the dielectric layer.

Abstract translation: 本发明的目的是提供一种形成氧化物电介质层的方法，该电介质层通过施加溶胶 - 凝胶法形成，并且几乎不被蚀刻溶液损坏，并且具有优异的诸如大电容的介电特性。 为了达到上述目的，采用以下工序（a）〜（c）为特征的溶胶 - 凝胶法的氧化物介电层的形成方法。 方法（a）：制备用于制造瞄准氧化物介电层的溶胶 - 凝胶溶液的溶液制备方法。 方法（b）：其中在金属基材表面上涂覆溶胶 - 凝胶溶液的阶段，然后在含氧气氛中干燥，然后依次在含氧气氛中热解的步骤为一个单位步骤; 一个单位步骤重复两次或更多次; 并且在惰性气体取代气氛等中在550℃〜1000℃的预烘烤阶段可选地设置在一个单元步骤和下一个单元步骤之间，以控制膜厚度。 方法（c）：在惰性气体取代气氛等中，在550℃〜1000℃下对经涂布的金属基材进行烘烤处理的烧成工序，以完成电介质层。

公开(公告)号：US07435675B2

公开(公告)日：2008-10-14

申请号：US11479400

申请日：2006-06-30

Applicant: Huankiat Seh ,  Yongki Min

Inventor： Huankiat Seh ,  Yongki Min

IPC: H01L21/4763

CPC classification number: H05K1/162 ,  H05K1/112 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09763 ,  H05K2203/0113 ,  H05K2203/0353 ,  H05K2203/061

Abstract: A method of forming a pre-patterned high-k dielectric film onto a support layer. The method includes: providing a support layer; providing a template defining template openings therein exhibiting a pattern that is a mirror image of a pattern of the pre-patterned high-k dielectric film; disposing the template onto the support layer; providing a high-k precursor material inside the template openings; curing the high-k precursor material inside the template openings to yield a cured film; and removing the template from the support layer after curing to leave the cured film on the conductive film.

Abstract translation: 将预图案化的高k电介质膜形成在支撑层上的方法。 该方法包括：提供支撑层; 提供其中示出模板开口的模板，其中显示作为预图案化高k电介质膜的图案的镜像的图案; 将模板设置在支撑层上; 在模板开口内提供高k前体材料; 固化模板开口内的高k前体材料以产生固化膜; 并且在固化之后从支撑层去除模板以将固化膜留在导电膜上。

公开(公告)号：US20080158770A1

公开(公告)日：2008-07-03

申请号：US12000125

申请日：2007-12-10

Applicant: In Hyung Lee ,  Yul Kyo Chung ,  Bae Kyun Kim ,  Seung Eun Lee ,  Jung Won Lee

Inventor： In Hyung Lee ,  Yul Kyo Chung ,  Bae Kyun Kim ,  Seung Eun Lee ,  Jung Won Lee

IPC: H01G4/00 ,  H05K3/30

CPC classification number: H05K1/162 ,  H01G4/005 ,  H01G4/33 ,  H05K3/046 ,  H05K2201/0108 ,  H05K2201/0175 ,  H05K2203/016 ,  H05K2203/0528 ,  H05K2203/0537 ,  H05K2203/107 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A method of manufacturing a circuit board embedding a thin film capacitor, the method including: forming a sacrificial layer on a first substrate; forming a dielectric layer on the sacrificial layer; forming a first electrode layer on the dielectric layer; disposing the first substrate on the second substrate in such a way that the first electrode layer is bonded to a top of a second substrate; decomposing the sacrificial layer by irradiating a laser beam onto the sacrificial layer through the first substrate; separating the first substrate from the second substrate; and forming a second electrode layer on the dielectric layer.

Abstract translation: 一种制造嵌入薄膜电容器的电路板的方法，所述方法包括：在第一基板上形成牺牲层; 在所述牺牲层上形成介电层; 在所述电介质层上形成第一电极层; 将第一基板设置在第二基板上，使得第一电极层接合到第二基板的顶部; 通过经由所述第一基板将激光束照射到所述牺牲层上来分解所述牺牲层; 将第一基板与第二基板分离; 以及在所述电介质层上形成第二电极层。

公开(公告)号：US20080054403A1

公开(公告)日：2008-03-06

申请号：US11929788

申请日：2007-10-30

Applicant: Cengiz Palanduz

Inventor： Cengiz Palanduz

IPC: H01L29/76

CPC classification number: H05K1/162 ,  H01G4/1209 ,  H01G4/20 ,  H01G4/33 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K2201/0175 ,  H05K2201/0195 ,  H05K2201/0326 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49155 ,  H01L2924/00

Abstract: An apparatus including a first electrode; a second electrode; a first and second ceramic material disposed between the first electrode and the second electrode, the second ceramic material having a greater electrical conductivity than the first ceramic material. A method including forming a first ceramic material film and a different second ceramic material film on a first electrode; and forming a second electrode on the second ceramic material film to form a capacitor structure having the first ceramic material film and the second ceramic material film disposed between the first electrode and the second electrode, wherein the first ceramic material has a conductivity selected to dampen undesired oscillations in electrical device operation to which the capacitor structure may be exposed. An apparatus including a first electrode; a second electrode; and a composite dielectric including a plurality of dielectric films including a different Curie temperature.

公开(公告)号：US20070178412A1

公开(公告)日：2007-08-02

申请号：US11700864

申请日：2007-02-01

Applicant: Hyung Mi Jung ,  Yul Kyo Chung ,  Hyung Dong Kang

Inventor： Hyung Mi Jung ,  Yul Kyo Chung ,  Hyung Dong Kang

IPC: G03C5/00

CPC classification number: H05K1/162 ,  H05K3/16 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763

Abstract: In a method for manufacturing a printed circuit board with a thin film capacitor embedded therein, a conductive metal is sputtered via a first mask to form a lower electrode. A dielectric material is sputtered via a second mask to form a dielectric layer. The conductive metal is sputtered via a third mask to form an upper electrode. An insulating layer is stacked on a stack body with the upper electrode formed therein and via holes are perforated from a top surface of the insulating layer to a top surface of the lower electrode and from the top surface of the insulating layer to a top surface of the upper electrode formed on the substrate. Also, the stack body with the via holes formed therein is electrolytically and electrolessly plated.

Abstract translation: 在其中嵌入有薄膜电容器的印刷电路板的制造方法中，通过第一掩模溅射导电金属以形成下电极。 通过第二掩模溅射介电材料以形成电介质层。 通过第三掩模溅射导电金属以形成上电极。 绝缘层堆积在堆叠体上，上电极形成在其中，并且通孔从绝缘层的顶表面穿孔到下电极的顶表面，并从绝缘层的顶表面到 上电极形成在基板上。 此外，其中形成有通孔的堆叠体是电解和无电镀的。

公开(公告)号：US20070151758A1

公开(公告)日：2007-07-05

申请号：US11323515

申请日：2005-12-30

Applicant: Gregory Dunn ,  Jaroslaw Magera ,  Jovica Savic

Inventor： Gregory Dunn ,  Jaroslaw Magera ,  Jovica Savic

IPC: H05K1/11 ,  H01R12/04

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09718

Abstract: A method is for fabricating an embedded capacitance printed circuit board assembly (400, 1100). The embedded capacitance printed circuit board assembly includes two embedded capacitance structures (110). Each capacitance structure (110) includes a crystallized dielectric oxide layer (115) sandwiched between an outer electrode layer (120) and an inner electrode layer (125) in which the two inner electrode layers are electrically connected together. A rivet via (1315) and a stacked via (1110) formed from a button via (910) and a stacked blind via (1111) may be used to electrically connect the two inner electrode layers together. A spindle via (525) may be formed through the inner and outer layers. The multi-layer printed circuit board may be formed from a capacitive laminate (100) that includes two capacitance structures.

Abstract translation: 一种用于制造嵌入式电容印刷电路板组件（400,1100）的方法。 嵌入式电容印刷电路板组件包括两个嵌入式电容结构（110）。 每个电容结构（110）包括夹在两个内部电极层电连接在一起的外部电极层（120）和内部电极层（125）之间的结晶化电介质氧化物层（115）。 可以使用铆钉通孔（1315）和由按钮通孔（910）和堆叠的通孔（1111）形成的堆叠通孔（1110）将两个内部电极层电连接在一起。 主轴通孔（525）可以通过内层和外层形成。 多层印刷电路板可以由包括两个电容结构的电容层压板（100）形成。

公开(公告)号：US07224571B2

公开(公告)日：2007-05-29

申请号：US11218357

申请日：2005-09-02

Applicant: Sriram Srinivasan ,  John S. Guzek ,  Cengiz A. Palanduz ,  Victor Prokofiev ,  Joel A. Auernheimer

Inventor： Sriram Srinivasan ,  John S. Guzek ,  Cengiz A. Palanduz ,  Victor Prokofiev ,  Joel A. Auernheimer

IPC: H01G4/228

CPC classification number: H05K1/162 ,  H01G4/10 ,  H01G4/1209 ,  H01G4/33 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09309 ,  Y10T29/43 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a substrate core by attaching a first dielectric layer to a second conductive layer of a thin film capacitor, and attaching a second dielectric layer to a first conductive layer of the thin film capacitor.

Abstract translation: 描述形成微电子结构的方法。 这些方法的实施例包括通过将第一电介质层附着到薄膜电容器的第二导电层并且将第二电介质层附接到薄膜电容器的第一导电层来形成衬底芯。

公开(公告)号：US20070105278A1

公开(公告)日：2007-05-10

申请号：US11615495

申请日：2006-12-22

Applicant: Takashi Kariya ,  Akira Mochida

Inventor： Takashi Kariya ,  Akira Mochida

IPC: H01L21/00 ,  H01L23/02

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2224/05001 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2203/0353 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: In a printed wiring board 10, an upper electrode connecting portion 52 penetrates through a capacitor portion 40 in top to bottom direction so that an upper electrode connecting portion first part 52a is not in contact with the capacitor portion 40, passes through an upper electrode connecting portion third part 52c provided at the upper portion of the capacitor portion 40, and then connects from the upper electrode connecting portion second part 52b to an upper electrode 42. Furthermore, a lower electrode connecting portion 51 penetrates through the capacitor portion 40 in top to bottom direction so that it is not in contact with the upper electrode 42 of the capacitor portion 40, but is in contact with a lower electrode 41. Therefore, the upper electrode connecting portion 52 and the lower electrode connecting portion 51 can be formed even after in process of build-up, the whole surface is covered by a high dielectric capacitor sheet that has a structure that a high dielectric layer is sandwiched between two metal foils and will afterwards serve as the capacitor portion 40.

Abstract translation: 在印刷布线板10中，上部电极连接部52从上下方向贯穿电容器部40，使上部电极连接部第一部分52a不与电容器部40接触，通过上部电极 连接部分第三部分52c设置在电容器部分40的上部，然后从上电极连接部分第二部分52b连接到上电极42。 此外，下电极连接部51从上下方向贯通电容器部40，使其不与电容器部40的上部电极42接触，而与下部电极41接触。 因此，上部电极连接部52和下部电极连接部51即使在积聚的过程中也可以形成，整个表面被高介电电容器片覆盖，该介电电容片具有将介电层夹在高介电层之间的结构 两个金属箔，然后用作电容器部分40。