公开(公告)号：US06439115B1

公开(公告)日：2002-08-27

申请号：US09650840

申请日：2000-08-30

Applicant: John M. Michiels ,  Darryl M. Stansbury

Inventor： John M. Michiels ,  Darryl M. Stansbury

IPC: B41M112

CPC classification number: B41M1/12 ,  B41M1/34 ,  B41M3/006 ,  H01J29/92 ,  H01L51/0004 ,  H05K1/092 ,  H05K1/181 ,  H05K3/1233 ,  H05K3/248 ,  H05K3/4664 ,  H05K2201/035 ,  H05K2201/09045 ,  H05K2201/09981 ,  H05K2203/0264

Abstract: Method for screen printing a continuous structure on a substrate wherein the screen printed structure extends from at least a first level to at least a second level. The disclosed method is particularly suitable for the fabrication of microelectronic devices and components thereof including the fabrication of field emission display devices. Preferably, a print screen of a preferred thickness having a preconfigured print pattern formed therethrough, in combination with a squeegee having a hardness within a preferred range, are used to force a screen printable substance onto a substrate while maintaining a portion of the print screen within a preferred reference angle. The resulting screen printed structure extends from at least one lower level to at least one upper level in a continuous “uphill” manner. The disclosed method is particularly suitable for forming continuous electrically conductive structures or circuit traces extending from a lower level of a substrate, such as an anode plate of an FED device, up onto at least one second surface vertically distanced from the substrate. The electrically conductive structure may optionally terminate into a specifically configured contact pad for accommodating complimentary contacting structures located on a mating component, such as a cathode plate of an FED device.

公开(公告)号：US20020104369A1

公开(公告)日：2002-08-08

申请号：US10067952

申请日：2002-02-05

Applicant: Interlink Electronics, Inc.

Inventor： Jeffrey R. Baker ,  Carlos S. Sanchez

IPC: G01N007/00

CPC classification number: H01H13/702 ,  G01L1/20 ,  G01L1/205 ,  H01H2201/036 ,  H01H2203/02 ,  H01H2239/01 ,  H05K1/0268 ,  H05K1/11 ,  H05K1/141 ,  H05K1/167 ,  H05K3/249 ,  H05K3/305 ,  H05K3/365 ,  H05K2201/035 ,  H05K2201/09663 ,  H05K2201/10151 ,  H05K2201/2036 ,  H05K2203/0278 ,  Y10T29/49002 ,  Y10T29/49007 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49146

Abstract: The cost and complexity of an electronic pressure sensitive transducer are decreased by constructing such a transducer directly on a printed circuit board containing support electronics. Conductive traces are formed on the printed circuit board to define a contact area. A flexible substrate having an inner surface is positioned over the contact area. An adhesive spacer, substantially surrounding the contact area, attaches the flexible substrate to the printed circuit board. At least one resistive layer is deposited on the flexible substrate inner surface. In use, the resistive layer contacts at least two conductive traces in response to pressure applied to the flexible substrate to produce an electrical signal indicative of applied pressure.

Abstract translation: 电子压敏传感器的成本和复杂性通过直接在包含支撑电子器件的印刷电路板上构建这样的传感器来减少。 导电迹线形成在印刷电路板上以限定接触区域。 具有内表面的柔性基板位于接触区域上方。 基本上围绕接触区域的粘合剂间隔件将柔性基板附接到印刷电路板。 至少一个电阻层沉积在柔性衬底内表面上。 在使用中，电阻层响应于施加到柔性衬底的压力而接触至少两个导电迹线，以产生指示所施加的压力的电信号。

公开(公告)号：US20020022383A1

公开(公告)日：2002-02-21

申请号：US09908545

申请日：2001-07-20

Inventor： Tsuyoshi Sakata ,  Takashi Nagawatari

IPC: H05K001/00

CPC classification number: H01R12/52 ,  H01R12/7082 ,  H01R12/714 ,  H01R13/2414 ,  H05K1/095 ,  H05K3/326 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0314 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/0959 ,  H05K2201/10378

Abstract: A compression connector (10) comprises an insulation sheet (11) having a plurality of retention holes, a plurality of elastic contacts (12) provided in the retention holes to make elastic contact with a pair of boards (20) and (30) and a printed line (13) provided on at least one face of the insulation sheet (11) to connect the elastic contacts (12).

Abstract translation: 压缩连接器（10）包括具有多个保持孔的绝缘片（11），设置在保持孔中以与一对板（20）和（30）弹性接触的多个弹性触点（12），以及 设置在所述绝缘片（11）的至少一个面上以连接所述弹性接触件（12）的印刷线（13）。

公开(公告)号：US20010025874A1

公开(公告)日：2001-10-04

申请号：US09819518

申请日：2001-03-27

Applicant: NEC Corporation

Inventor： Tomohiro Nishiyama

IPC: B23K031/02 ,  B23K001/20 ,  B23K035/12

CPC classification number: H05K3/3436 ,  B23K1/0016 ,  B23K35/3613 ,  B23K2101/40 ,  H01L24/11 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H05K3/3478 ,  H05K2201/035 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/0338 ,  H05K2203/041 ,  Y02P70/613 ,  H01L2924/00

Abstract: Solder balls are mounted on electrodes with an active resin therebetween. The solder is heated and melts to be connected to pads of an LSI chip, thereby forming solder bumps on the chip. In a method of forming bumps, a method of mounting flip chips, and a mounting structure, by the use of the active resin, a flux washing process can be eliminated and at the same time, an assembly cost can be minimized.

Abstract translation: 焊球安装在其间具有活性树脂的电极上。 焊料被加热并熔化以连接到LSI芯片的焊盘，从而在芯片上形成焊料凸块。 在形成凸块的方法中，通过使用活性树脂安装倒装芯片和安装结构的方法可以消除助焊剂清洗过程，同时可以最小化组装成本。

公开(公告)号：US06284080B1

公开(公告)日：2001-09-04

申请号：US09626415

申请日：2000-07-26

Applicant: Samuel F. Haq ,  Patrick F. Malone ,  Donald P. Varner

Inventor： Samuel F. Haq ,  Patrick F. Malone ,  Donald P. Varner

IPC: B32B3126

CPC classification number: H01L23/49883 ,  A61N1/02 ,  A61N1/375 ,  H01L21/4857 ,  H01L21/4867 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/248 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4676 ,  H05K2201/035 ,  Y10S428/901 ,  Y10T29/49163 ,  Y10T428/24926 ,  H01L2924/00

Abstract: The present invention relates to multi-layer ceramic packaging of hybrid micro-electronic devices, including those for implantable medical devices. The invention permits size reduction and design simplification in such packaging by eliminating the need for electrolytic or electroless plating, and by eliminating or substantially eliminating the shrinkage variation typically associated with surface metallization techniques.

Abstract translation: 本发明涉及混合微电子器件的多层陶瓷封装，包括可植入医疗器件的多层陶瓷封装。 本发明通过消除对电解或无电镀的需要以及通过消除或基本上消除通常与表面金属化技术相关的收缩变化，允许这种包装中的尺寸减小和设计简化。

公开(公告)号：US20010006116A1

公开(公告)日：2001-07-05

申请号：US09766011

申请日：2001-01-18

Applicant: International Business Machines Corporation

Inventor： James M. Blazick ,  Michael E. Cropp ,  James N. Humenik ,  Gerald H. Leino ,  Jawahar P. Nayak ,  Frank V. Ranalli ,  Deborah A. Sylvester ,  John A. Trumpetto ,  James C. Utter ,  Rao V. Vallabhaneni ,  Renne L. Weisman

IPC: H05K001/16

CPC classification number: H05K3/1233 ,  H01L51/0004 ,  H05K3/245 ,  H05K2201/035 ,  H05K2203/0139

Abstract: A process of forming a multi-layer feature on a ceramic or organic article in which first and second layers of paste are sequentially screened through a screening mask wherein the screening mask has not been moved between screening steps. A structure produced by this process is also disclosed.

Abstract translation: 在陶瓷或有机制品上形成多层特征的方法，其中第一和第二层浆料通过筛选掩模被顺序地筛选，其中筛选掩模在筛选步骤之间没有移动。 还公开了通过该方法生产的结构。

公开(公告)号：US06218736B1

公开(公告)日：2001-04-17

申请号：US09332968

申请日：1999-06-15

Applicant: Yuji Yagi ,  Takeo Yasuho

Inventor： Yuji Yagi ,  Takeo Yasuho

IPC: H01L2348

CPC classification number: H05K3/4647 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/092 ,  H05K1/095 ,  H05K3/207 ,  H05K3/22 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4061 ,  H05K3/4069 ,  H05K3/4664 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2203/0113 ,  H05K2203/025 ,  H05K2203/0307 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A circuit board with protrusions at desired locations on a wiring pattern that on the surface of the board. The protrusions are made of the same conductive material used in the wiring pattern, and formed unitarily and simultaneously with the wiring pattern. Conductive material is filled into grooves having different depths and formed on a film. The filled conductive material is transferred onto the board, and then fired. Thus the circuit board is manufactured. Semiconductor devices and general-purpose components are mounted on the circuit board, whereby a semiconductor device can be manufactured with high reliability and at an inexpensive cost.

Abstract translation: 电路板，其在板的表面上的布线图案上的期望位置处具有突起。 突起由与布线图案相同的导电材料制成，并且与布线图案一体形成。 将导电材料填充到具有不同深度的凹槽中并形成在膜上。 将填充的导电材料转移到板上，然后烧制。 因此制造电路板。 半导体器件和通用部件安装在电路板上，由此可以以高可靠性和廉价的成本制造半导体器件。

公开(公告)号：US6162664A

公开(公告)日：2000-12-19

申请号：US168886

申请日：1998-10-09

Applicant: Jin-Sung Kim

Inventor： Jin-Sung Kim

IPC: H01L23/12 ,  H01L23/13 ,  H01L23/24 ,  H01L23/28 ,  H01L23/31 ,  H01L23/498 ,  H05K3/34 ,  H01L21/50 ,  H01L21/44

CPC classification number: H01L23/49866 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3121 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2203/043 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A solder structure for a surface mounting type semiconductor chip package, and a method of fabricating the same are disclosed. The surface mounting type semiconductor chip package includes a package body having an interconnection formed therein and a semiconductor chip accommodated therein, and a plurality of double layer bumps each attached to the bottom of the package body as an external connection terminal.

Abstract translation: 公开了一种用于表面安装型半导体芯片封装的焊料结构及其制造方法。 表面安装型半导体芯片封装包括具有形成在其中的互连的封装主体和容纳在其中的半导体芯片，以及多个双层凸块，每个双层凸块均附接到封装主体的底部作为外部连接端子。

公开(公告)号：US06049977A

公开(公告)日：2000-04-18

申请号：US856991

申请日：1997-05-15

Applicant: Glen G. Atkins ,  Michael S. Cohen ,  Karl H. Mauritz ,  James M. Shaffer

Inventor： Glen G. Atkins ,  Michael S. Cohen ,  Karl H. Mauritz ,  James M. Shaffer

IPC: G01R31/28 ,  H05K1/09 ,  H05K3/34 ,  H05K3/40 ,  H01R9/09

CPC classification number: G01R31/2862 ,  G01R31/2886 ,  H05K3/4007 ,  G01R31/2863 ,  H05K1/095 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K3/3457 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method of forming electrically conductive pillars on a printed circuit board by providing a printed circuit board having a plurality of electrical traces and forming a plurality of elongate, electrically conductive pillars of superimposed layers of solder and conductive polymer on the printed circuit board. The elongate, electrically conductive pillars are connected by a first end to the electrical traces of the printed circuit board and extend substantially perpendicularly from the printed circuit board such that a second end of each of the plurality of elongate, electrically conductive pillars lies in substantially a common plane which is substantially perpendicular to and above said printed circuit board.

Abstract translation: 一种在印刷电路板上形成导电柱的方法，该方法是通过提供具有多个电迹线的印刷电路板，并在印刷电路板上形成多个细长导电的叠层焊料和导电聚合物的导电柱。 细长的导电柱通过第一端连接到印刷电路板的电迹线并且从印刷电路板基本上垂直地延伸，使得多个细长导电柱中的每一个的第二端基本上位于 基本上垂直于所述印刷电路板上方的公共平面。

公开(公告)号：US6041496A

公开(公告)日：2000-03-28

申请号：US22320

申请日：1998-02-11

Applicant: Samuel F. Haq ,  Patrick F. Malone ,  John H. Fortney ,  Donald P. Varner

Inventor： Samuel F. Haq ,  Patrick F. Malone ,  John H. Fortney ,  Donald P. Varner

IPC: A61N1/02 ,  A61N1/375 ,  H01L21/48 ,  H01L23/498 ,  H05K1/00 ,  H05K1/03 ,  H05K1/09 ,  H05K3/24 ,  H05K3/40 ,  H05K3/46 ,  H01R3/10

CPC classification number: A61N1/02 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/49883 ,  H05K3/4061 ,  A61N1/375 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/035 ,  H05K3/248 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4676 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: The present invention relates to multi-layer ceramic packaging of hybrid micro-electronic devices, including those for implantable medical devices. The invention permits size reduction and design simplification in such packaging by eliminating the need for electrolytic or electroless plating, and by eliminating or substantially eliminating the shrinkage variation typically associated with surface metallization techniques.

Abstract translation: 本发明涉及混合微电子器件的多层陶瓷封装，包括可植入医疗器件的多层陶瓷封装。 本发明通过消除对电解或无电镀的需要以及通过消除或基本上消除通常与表面金属化技术相关的收缩变化，允许这种包装中的尺寸减小和设计简化。