公开(公告)号：US20120273258A1

公开(公告)日：2012-11-01

申请号：US13156359

申请日：2011-06-09

Applicant: YUNG-CHIEH CHEN ,  SHOU-KUO HSU ,  HSIEN-CHUAN LIANG ,  SHIN-TING YEN ,  DAN-CHEN WU

Inventor： YUNG-CHIEH CHEN ,  SHOU-KUO HSU ,  HSIEN-CHUAN LIANG ,  SHIN-TING YEN ,  DAN-CHEN WU

IPC: H05K1/09

CPC classification number: H05K1/0251 ,  H05K1/0245 ,  H05K2201/09309 ,  H05K2201/09672 ,  H05K2201/09836

Abstract: A printed circuit board includes a first signal layer, a first reference layer, a second signal layer, and a third signal layer in that order and includes a first slanted via and a second slanted via. The first signal layer includes an parallel first transmission wire and a second transmission wire. The first and second transmission wires are coupled with each other and cooperatively constitute a first differential pair with an edge-coupled structure. The second signal layer includes a third transmission wire. The third signal layer includes a fourth transmission wire parallel to and coupled with the third transmission wire. The third and fourth transmission wires cooperatively constitute a second differential pair with a broadside-coupled structure. The first slanted via obliquely are interconnected between the first transmission wire and the third transmission wire. The second slanted via obliquely are interconnected between the second transmission wire and the fourth transmission wire.

Abstract translation: 印刷电路板依次包括第一信号层，第一参考层，第二信号层和第三信号层，并且包括第一倾斜通孔和第二倾斜通孔。 第一信号层包括并行的第一传输线和第二传输线。 第一和第二传输线彼此耦合并协同地构成具有边缘耦合结构的第一差分对。 第二信号层包括第三传输线。 第三信号层包括与第三传输线并联并与第三传输线耦合的第四传输线。 第三和第四传输线协作地构成具有宽边耦合结构的第二差分对。 第一倾斜地倾斜地在第一传输线和第三传输线之间互连。 第二倾斜地倾斜地在第二传输线和第四传输线之间互连。

公开(公告)号：US20120235764A1

公开(公告)日：2012-09-20

申请号：US13365491

申请日：2012-02-03

Applicant: Sae Kyoung KANG ,  Joon Ki LEE ,  Joon Young HUH ,  Jyung Chan LEE

Inventor： Sae Kyoung KANG ,  Joon Ki LEE ,  Joon Young HUH ,  Jyung Chan LEE

IPC: H01P3/08 ,  H05K3/10 ,  H03H7/38

CPC classification number: H01P3/006 ,  H01P5/028 ,  H05K1/0219 ,  H05K1/0227 ,  H05K1/0253 ,  H05K1/147 ,  H05K2201/058 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/10121 ,  Y10T29/49155

Abstract: Disclosed is a structure for impedance matching by applying a CPW structure to an impedance discontinuous portion on a data signal line or using a micro-strip open stub so as to be used for high-speed transmission by a flexible PCB. According to the present invention, it is possible to fabricate a flexible PCB capable of performing low-priced and high-speed transmission.

Abstract translation: 公开了通过将CPW结构应用于数据信号线上的阻抗不连续部分或使用微带开路短截线来进行阻抗匹配的结构，以便用于通过柔性PCB的高速传输。 根据本发明，可以制造能够执行低价和高速传输的柔性PCB。

公开(公告)号：US20120231664A1

公开(公告)日：2012-09-13

申请号：US13473787

申请日：2012-05-17

Applicant: Frank M. Straka ,  Ronald L. Tellas

Inventor： Frank M. Straka ,  Ronald L. Tellas

IPC: H01R13/66

CPC classification number: H01R13/6466 ,  H01R4/2425 ,  H01R13/6625 ,  H01R13/6658 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/118 ,  H05K1/147 ,  H05K1/162 ,  H05K2201/09172 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A communication jack has a housing with a face having a plug receiving aperture. A plurality of conductive path pairs extends from corresponding plug interface contacts located at the plug receiving aperture to corresponding output terminals. A first circuit board is connected to the plug interface contacts and a second circuit board is connected to the plug interface contacts and the output terminals. The first circuit board has a first single stage of crosstalk compensation with opposite polarity of the crosstalk of a plug for a first combination of the conductive path pairs. The second circuit board includes a second single stage of opposite polarity crosstalk compensation for some of the conductive path pairs not compensated on the first circuit board. The stages cancel substantially all of the crosstalk caused by the plug, for the signal operating frequencies, for corresponding combinations of the conductive path pairs.

Abstract translation: 通信插座具有带有插头接收孔的面的壳体。 多个导电路径对从位于插头接收孔处的相应插头接口触头延伸到对应的输出端子。 第一电路板连接到插头接口触点，第二电路板连接到插头接口触点和输出端子。 第一电路板具有与导电路径对的第一组合的插头的串扰极性相反的串扰补偿的第一单级。 第二电路板包括用于在第一电路板上未补偿的一些导电路径对的相反极性串扰补偿的第二单级。 针对信号工作频率，对于导电路径对的相应组合，这些级基本上消除了由插头引起的串扰。

公开(公告)号：US08262415B2

公开(公告)日：2012-09-11

申请号：US12969779

申请日：2010-12-16

Applicant: Jack E. Caveney ,  Masud Bolouri-Saransar

Inventor： Jack E. Caveney ,  Masud Bolouri-Saransar

IPC: H01R13/66

CPC classification number: H01R13/6461 ,  H01R13/6464 ,  H01R13/6466 ,  H01R13/66 ,  H01R13/6658 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A communication jack having crosstalk compensation features for overall crosstalk interference reduction is disclosed. In one embodiment, the jack is configured to receive a plug to form a communication connection, and comprises jack contacts disposed in the jack, with each contact having at least a first surface and a second surface. Upon the plug being received by the jack, the plug contacts interface with the first surface of the jack contacts. The jack further includes a first capacitive coupling connected between two pairs of jack contacts to compensate for near end crosstalk, with the first capacitive coupling being connected to the pairs of jack contacts along the second surface adjacent to where the plug contacts interface with the jack contacts. A far end crosstalk compensation scheme is also set forth.

Abstract translation: 公开了一种具有用于整个串扰干扰减少的串扰补偿特征的通信插座。 在一个实施例中，千斤顶配置成接收插头以形成通信连接，并且包括设置在插座中的插座触点，每个触头具有至少第一表面和第二表面。 当插头被插座接收时，插头触点与插座触点的第一表面接触。 插座还包括连接在两对插座触点之间的第一电容耦合器，以补偿近端串扰，第一电容耦合器沿着与插座触头与插座触头相接触的第二表面连接到插座触点对 。 还提出了远端串扰补偿方案。

公开(公告)号：US08254136B2

公开(公告)日：2012-08-28

申请号：US12204015

申请日：2008-09-04

Applicant: Kwan-Ho Kim ,  Ick-Kyu Jang ,  Ji-Man Myeong

Inventor： Kwan-Ho Kim ,  Ick-Kyu Jang ,  Ji-Man Myeong

IPC: G09G3/36 ,  G06F3/038 ,  G02F1/1345 ,  H05K3/36

CPC classification number: H05K1/0219 ,  G09G3/3696 ,  G09G2330/06 ,  H05K1/0218 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09672 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49156

Abstract: A printed circuit board (“PCB”) includes a first pattern structure, a second pattern structure, a third pattern structure, and a fourth pattern structure. The first pattern structure includes a first ground pattern. The second pattern structure includes a first line pattern overlapping the first ground pattern and a second ground pattern electrically insulated from the first line pattern. The third pattern structure includes a third ground pattern overlapping the first line pattern and a second line pattern overlapping the second ground pattern. The fourth pattern structure includes a fourth ground pattern overlapping the second line pattern. Therefore, the PCB may decrease noise.

Abstract translation: 印刷电路板（“PCB”）包括第一图案结构，第二图案结构，第三图案结构和第四图案结构。 第一图案结构包括第一接地图案​​。 第二图案结构包括与第一接地图案​​重叠的第一线图案和与第一线图案电绝缘的第二接地图案。 第三图案结构包括与第一线图案重叠的第三接地图案和与第二接地图案重叠的第二线图案。 第四图案结构包括与第二线图案重叠的第四接地图案。 因此，PCB可能会降低噪音。

公开(公告)号：US08203206B2

公开(公告)日：2012-06-19

申请号：US13023959

申请日：2011-02-09

Applicant: Zhaoqing Chen ,  Christian Schuster

Inventor： Zhaoqing Chen ,  Christian Schuster

IPC: H01L23/48 ,  H01L23/04

CPC classification number: H01L23/5222 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/09672 ,  H01L2924/00

Abstract: An electrical device includes a plurality of interconnects passing through a plane. The interconnects have a longitudinal axis substantially perpendicular to the plane and including an arrangement pattern which reduces or eliminates cross-talk between nearest neighboring interconnects, wherein the interconnects include a first differentially driven signal conductor pair and at least one other signal conductor, and the arrangement includes the at least one other signal conductor disposed at a substantially same distance from each conductor of the first differentially driven signal conductor pair.

Abstract translation: 电气装置包括通过平面的多个互连件。 互连具有基本上垂直于平面的纵向轴线并且包括减少或消除最近相邻互连件之间的串扰的布置图案，其中互连包括第一差分驱动信号导体对和至少一个其它信号导体，并且布置 包括设置在与第一差分驱动信号导体对的每个导体基本相同的距离处的至少一个其它信号导体。

公开(公告)号：US08193898B2

公开(公告)日：2012-06-05

申请号：US12529700

申请日：2008-02-28

Applicant: Isao Tonouchi

Inventor： Isao Tonouchi

IPC: H01C7/18

CPC classification number: H01C1/14 ,  H01C7/003 ,  H01C7/18 ,  H01C17/28 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/167 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09672 ,  H05K2201/0979

Abstract: A laminated body and fabrication method thereof, which allow space saving and control of variation in internal layer resistance, are provided. When forming an internal-layer resistive element 7 in a multilayer ceramic substrate 10, the internal-layer resistive element 7 is connected to exterior electrodes (an upper surface electrode 32 and an undersurface electrode 34) via multiple via-electrodes 3a and 3b arranged in parallel, without a pad electrode adopted in the conventional laminated body. Moreover, in a multilayer ceramic substrate having multiple internal-layer resistive elements arranged in a multilayer structure, multiple internal-layer resistive elements are directly connected via multiple via-electrodes arranged in parallel.

Abstract translation: 提供了能够节省空间并控制内层电阻的变化的层叠体及其制造方法。 当在多层陶瓷衬底10中形成内层电阻元件7时，内层电阻元件7通过多个通孔电极3a和3b连接到外电极（上表面电极32和下表面电极34） 平行的，在常规层压体中没有采用焊盘电极。 此外，在具有以多层结构排列的多个内层电阻元件的多层陶瓷基板中，多个内层电阻元件通过并联布置的多个通孔电极直接连接。

公开(公告)号：US08174840B2

公开(公告)日：2012-05-08

申请号：US12260254

申请日：2008-10-29

Applicant: Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

Inventor： Uei-Ming Jow ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Ying-Jiunn Lai

IPC: H05K1/16

CPC classification number: H01L23/14 ,  H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01G4/30 ,  H01G4/40 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49894 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/086 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A multi-functional composite substrate structure is provided. The first substrate with high dielectric constant and the second substrate with low dielectric constant and low loss tangent are interlaced above the third substrate. One or more permeance blocks may be formed above each substrate, so that one or more inductors may be fabricated thereon. One or more capacitors may be fabricated on the first substrate. Also, one or more signal transmission traces of the system impedance are formed on the second substrate of the outside layer. Therefore, the inductance of the inductor(s) is effectively enhanced. Moreover, the area of built-in components is reduced. Furthermore, it has shorter delay time, smaller dielectric loss, and better return loss for the transmission of high speed and high frequency signal.

Abstract translation: 提供了多功能复合基板结构。 具有高介电常数的第一衬底和具有低介电常数和低损耗角正切的第二衬底交错在第三衬底之上。 一个或多个导磁块可以形成在每个衬底之上，使得可以在其上制造一个或多个电感器。 可以在第一基板上制造一个或多个电容器。 此外，系统阻抗的一个或多个信号传输迹线形成在外层的第二基板上。 因此，有效地提高了电感器的电感。 此外，内置组件的面积减少。 此外，它具有更短的延迟时间，更小的介电损耗和更高的传输高速和高频信号的回波损耗。

公开(公告)号：US08110747B2

公开(公告)日：2012-02-07

申请号：US12430133

申请日：2009-04-27

Applicant: Shou-Kuo Hsu ,  Chia-Nan Pai

Inventor： Shou-Kuo Hsu ,  Chia-Nan Pai

IPC: H05K1/00

CPC classification number: H05K1/0245 ,  H05K1/0253 ,  H05K1/0393 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0969

Abstract: A flexible printed circuit board (FPCB) includes a signal layer, upper and lower ground layers, and two dielectric layers. The signal layer includes a differential pair comprising two transmission lines to transmit a pair of differential signals. The dielectric layers are located on and under the signal layer to sandwich the signal layer. The upper ground layer is attached to the dielectric layer on the signal layer, opposite to the signal layer. The lower ground layer is attached to the dielectric layer under the signal layer, opposite to the signal layer. Each ground layer includes a grounded sheet made of conductive material. Two voids are defined in each ground layer and located at opposite sides of the corresponding grounded sheet. Distances between the middle line of the grounded sheet of each ground layer and middle lines of the two transmission lines are equal.

Abstract translation: 柔性印刷电路板（FPCB）包括信号层，上下接地层和两个电介质层。 信号层包括差分对，该差分对包括用于发送一对差分信号的两条传输线。 电介质层位于信号层之上和之下，以夹住信号层。 上层接地层与信号层的电介质层相连，与信号层相反。 下部接地层附着在与信号层相反的信号层下面的电介质层上。 每个接地层包括由导电材料制成的接地片。 在每个接地层中定义两个空隙，并且位于相应接地片的相对侧。 每个接地层的接地片的中间线与两条传输线的中间线之间的距离相等。

公开(公告)号：US20120006584A1

公开(公告)日：2012-01-12

申请号：US12673440

申请日：2008-07-17

Applicant: Takashi Matsui ,  Motoji Shiota

Inventor： Takashi Matsui ,  Motoji Shiota

IPC: H05K1/09 ,  H05K1/16 ,  H05K1/11

CPC classification number: H05K1/117 ,  G02F1/1345 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/01019 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2201/094 ,  H05K2201/09436 ,  H05K2201/09672 ,  H05K2201/09709 ,  Y02P70/611

Abstract: A wiring board of the present invention (1) is arranged so that: pads (30) arranged in a plurality of rows include: first-row pads (30a) connected to first metal wires (10a) among metal wires (10); and second-row pads (30b) connected to second metal wires (10b) among the metal wires (10), the first metal wires (10a) being longer than the second metal wires (10b); and that each of the first connecting lines (10a) is formed so as to be separated from a corresponding one of the second-row pads (30b) by at least an insulating layer, and so as to extend not through a region between the corresponding second-row pad (30b) and a second-row pad (30b) adjacent to the corresponding second-row pad (30b), but through a region below the corresponding second-row pad (30b).

Abstract translation: 本发明的布线基板（1）的布置方式为：排列成多行的焊盘（30）包括：与金属线（10）之间的第一金属线（10a）连接的第一排焊盘（30a） 和连接到金属线（10）中的第二金属线（10b）的第二排焊盘（30b），第一金属线（10a）比第二金属线（10b）长; 并且所述第一连接线（10a）中的每一个形成为与至少一个绝缘层与所述第二排焊盘（30b）中的相应一个焊盘相隔离，并且不延伸通过所述第二焊盘 第二排衬垫（30b）和与相应的第二排衬垫（30b）相邻的第二排衬垫（30b），但是通过相应的第二排衬垫（30b）下方的区域。