公开(公告)号：US06221503B1

公开(公告)日：2001-04-24

申请号：US09382400

申请日：1999-08-24

Applicant: John Michael Cotte ,  Judith Marie Roldan ,  Carlos Juan Sambucetti ,  Ravi F. Saraf

Inventor： John Michael Cotte ,  Judith Marie Roldan ,  Carlos Juan Sambucetti ,  Ravi F. Saraf

IPC: B32B1502

CPC classification number: H01L24/12 ,  H01L23/49816 ,  H01L23/49883 ,  H01L24/11 ,  H01L24/83 ,  H01L2224/11822 ,  H01L2224/13099 ,  H01L2224/13311 ,  H01L2224/13411 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/81011 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/19043 ,  H05K3/284 ,  H05K3/288 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/035 ,  H05K2201/10977 ,  H05K2201/10992 ,  Y02P70/613 ,  Y10T29/49165 ,  Y10T428/12063 ,  Y10T428/12104 ,  Y10T428/12528 ,  Y10T428/12569 ,  Y10T428/12687 ,  Y10T428/12701 ,  Y10T428/12708 ,  Y10T428/12889 ,  Y10T428/31678 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A paste is described for capping electrodes with an oxide free metal layer incorporating a solvent, an unzippable polymer and particles. The electrode could be an interconnect such as a C4 bump. A method for forming a coating and for testing integrated circuit chips is also described. The invention overcomes the problem of interconnecting Pb containing electrodes that are covered with an insulating oxide on integrated circuit chips by coating the Pb containing electrode with Au to provide an oxide free surface for testing and interconnection.

公开(公告)号：US6127735A

公开(公告)日：2000-10-03

申请号：US710992

申请日：1996-09-25

Applicant: Daniel George Berger ,  Guy Paul Brouillette ,  David Hirsch Danovitch ,  Peter Alfred Gruber ,  Bruce Lee Humphrey ,  Michael Liehr ,  William Thomas Motsiff ,  Carlos Juan Sambucetti

Inventor： Daniel George Berger ,  Guy Paul Brouillette ,  David Hirsch Danovitch ,  Peter Alfred Gruber ,  Bruce Lee Humphrey ,  Michael Liehr ,  William Thomas Motsiff ,  Carlos Juan Sambucetti

IPC: B23K35/26 ,  H01L21/60 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/81 ,  H05K3/3436 ,  H05K3/3468 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11822 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13609 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H05K2201/0379 ,  H05K2201/10992 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/128 ,  H05K3/3463 ,  H05K3/3478 ,  Y02P70/613

Abstract: A method of forming interconnects on an electronic device that can be bonded to another electronic device at a low processing temperature can be carried out by depositing a first interconnect material on the electronic device forming protrusions and then depositing a second interconnect material to at least partially cover the protrusions, wherein the second interconnect material has a lower flow temperature than the first interconnect material. The method is carried out by flowing a molten solder into a mold having microcavities to fill the cavities and then allowed to solidify. The mold is then aligned with a silicon wafer containing chips deposited with high melting temperatures solder bumps such that each microcavity of the mold is aligned with each high melting temperature solder bump on the chip. The aligned mold/wafer assembly is then passed through a reflow furnace to effect the transfer of the low melting temperature solder in the mold cavities onto the tip of the high melting temperature solder bumps on the wafer. A dual metallurgical composition bump is thereby formed by the two different solder alloys.

Abstract translation: 可以在能够以低处理温度结合到另一电子设备的电子设备上形成互连的方法可以通过在形成突起的电子设备上沉积第一互连材料，然后沉积第二互连材料至少部分覆盖 所述突起，其中所述第二互连材料具有比所述第一互连材料低的流动温度。 该方法通过将熔融焊料流入具有微腔的模具中以填充空腔，然后使其固化来进行。 然后将模具与包含沉积有高熔点温度焊料凸块的芯片的硅晶片对准，使得模具的每个微腔与芯片上的每个高熔点温度焊料凸块对准。 然后将对准的模具/晶片组件通过回流炉，以将模腔中的低熔点焊料转移到晶片上的高熔点温度焊料凸块的尖端上。 由此由两种不同的焊料合金形成双金属组合物凸块。

公开(公告)号：US06076726A

公开(公告)日：2000-06-20

申请号：US108482

申请日：1998-07-01

Applicant: Mark Kenneth Hoffmeyer ,  Phillip Duane Isaacs

Inventor： Mark Kenneth Hoffmeyer ,  Phillip Duane Isaacs

IPC: B23K1/00 ,  H01R12/04 ,  H05K3/34 ,  B23K31/02

CPC classification number: H05K3/3436 ,  B23K1/0016 ,  H05K3/3463 ,  B23K2201/42 ,  H05K2201/09481 ,  H05K2201/09572 ,  H05K2201/10992 ,  H05K2201/2081 ,  H05K2203/043 ,  H05K2203/0455 ,  H05K3/3452 ,  H05K3/3484 ,  Y02P70/613

Abstract: Fine pitch area array packaging is achieved using a via-in-pad design within the area array attach portion of a printed circuit board (PCB). The limitation of the design is the wicking action, whereby solder applied to the capture pad contact surface is depleted by capillary action into the via hole when reflowed, causing insufficient solder to be present at the contact surface to effect reliable and repeatable electrical connections. In one implementation, an initial application of solder is applied to plug the via hole with a material having a higher final melting temperature than eutectic solder, thereby providing a stable plug. This plug is formed by the initial solder application that may be either a eutectic solder containing a third metal that forms intermetallic compounds, when reflowed, that elevate the liquidus temperature or a solder having a different formulation with an inherent higher melting temperature. An alternative implementation is to plate the via hole with a material, such as nickel, which prevents eutectic solder, applied to the via capture pad contact surface, from wetting the hole surface and being drawn away from the contact surface by capillary action. Thus, the solder, applied to the via capture pad and used to establish an electrical connection is not depleted.

Abstract translation: 使用在印刷电路板（PCB）的区域阵列附着部分内的通孔焊盘设计实现细间距区域阵列封装。 设计的限制是芯吸作用，由此当回流时，施加到捕获垫接触表面的焊料被毛细管作用通入通孔中，导致在接触表面处存在不足的焊料以实现可靠和可重复的电连接。 在一个实施方案中，施加焊料的初始应用以用比共晶焊料更高的最终熔融温度的材料堵塞通孔，从而提供稳定的插塞。 该插头由初始焊料应用形成，其可以是包含形成金属间化合物的第三金属的共晶焊料，当回流时，提高液相线温度的焊料或具有固有的较高熔融温度的不同配方的焊料。 另一种实施方案是用诸如镍的材料对通孔进行平板化，其防止施加到通孔捕获垫接触表面的共晶焊料润湿孔表面并通过毛细管作用从接触表面拉出。 因此，施加到通孔捕获垫并用于建立电连接的焊料不会耗尽。

公开(公告)号：US6013877A

公开(公告)日：2000-01-11

申请号：US41157

申请日：1998-03-12

Applicant: Yinon Degani ,  King Lien Tai

Inventor： Yinon Degani ,  King Lien Tai

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H05K1/18 ,  H05K3/34 ,  H01R9/09

CPC classification number: H01L23/49827 ,  H05K3/3436 ,  H05K3/3463 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/09572 ,  H05K2201/10666 ,  H05K2201/10992 ,  Y02P70/613

Abstract: The specification describes techniques for attaching double sided circuit boards having plated through holes to interconnection substrates using solder bump arrays. The through holes are filled with a high melting point solder which allows solder bumps to be located directly on the through hole thus saving board area and reducing the interconnection length.

公开(公告)号：US5920125A

公开(公告)日：1999-07-06

申请号：US853942

申请日：1997-05-09

Applicant: James Vernon Ellerson ,  Joseph Funari ,  Jack Arthur Varcoe

Inventor： James Vernon Ellerson ,  Joseph Funari ,  Jack Arthur Varcoe

IPC: H01L21/56 ,  H01L21/60 ,  H05K3/30 ,  H05K3/34 ,  H01L23/48

CPC classification number: H05K3/3436 ,  H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/13113 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/27438 ,  H01L2224/29011 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1579 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K3/305 ,  H05K3/3431 ,  H05K3/3452 ,  H05K3/3463 ,  Y02P70/613

Abstract: Solder interconnection for forming connections between an integrated semiconductor device and a carrier substrate is provided. Located on the carrier substrate are electrodes and located between the electrodes and integrated semiconductor device are solder connections that have a relatively low melting point such that when the device is in operation, the solder connection will liquify thereby permitting expansion compensation between the substrate and semiconductor device.

公开(公告)号：US5907903A

公开(公告)日：1999-06-01

申请号：US4523

申请日：1998-01-08

Applicant: Joseph George Ameen ,  Joseph Funari

Inventor： Joseph George Ameen ,  Joseph Funari

IPC: H05K3/34 ,  H05K3/36

CPC classification number: H01R12/52 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H05K2201/09481 ,  H05K2201/09572 ,  H05K2201/10666 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0455 ,  H05K2203/1115 ,  H05K3/3494 ,  Y10T29/49126

Abstract: The present invention provides multi-layer multi-chip circuit board comprising at least two ATAB carriers having chips thereon, stacked upon each other in a pyramid configuration and attached to a substrate, thus reducing the required area on the substrate for mounting components to form a circuit board.

Abstract translation: 本发明提供了多层多芯片电路板，其包括至少两个具有芯片的ATAB载体，它们以金字塔形结构彼此堆叠并且附接到基板，从而减少了用于安装部件以形成基板的所需面积 电路板。

公开(公告)号：US5890284A

公开(公告)日：1999-04-06

申请号：US978110

申请日：1997-11-25

Applicant: Richard L. Chartrand ,  Wai-Mon Ma ,  Roger A. Stinemire

Inventor： Richard L. Chartrand ,  Wai-Mon Ma ,  Roger A. Stinemire

IPC: H05K1/11 ,  H05K3/22 ,  H05K3/34 ,  H05K3/42 ,  H05K3/40

CPC classification number: H05K3/3436 ,  H05K1/114 ,  H05K3/225 ,  H05K2201/09581 ,  H05K2201/10287 ,  H05K2201/10295 ,  H05K2201/10734 ,  H05K2201/10962 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K3/3426 ,  H05K3/429 ,  Y02P70/613 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49149 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49167 ,  Y10T29/49728 ,  Y10T29/4973

Abstract: In aspect, the present invention is directed to a method of modifying a circuit board having at least one Ball Grid Array (BGA). The method includes removing the via portion of the BGA pad from the circuit board to sever the connection between the via and the circuit, attaching the pad connector to the circuit board, and connecting the pad connector to the circuit of the circuit board.

Abstract translation: 在本发明中，本发明涉及一种修改具有至少一个球栅阵列（BGA）的电路板的方法。 该方法包括从电路板去除BGA焊盘的通孔部分，以切断通孔和电路之间的连接，将焊盘连接器连接到电路板，以及将焊盘连接器连接到电路板的电路。

公开(公告)号：US5859470A

公开(公告)日：1999-01-12

申请号：US974493

申请日：1992-11-12

Applicant: James Vernon Ellerson ,  Joseph Funari ,  Jack Arthur Varcoe

Inventor： James Vernon Ellerson ,  Joseph Funari ,  Jack Arthur Varcoe

IPC: H01L21/56 ,  H01L21/60 ,  H05K3/30 ,  H05K3/34 ,  H01L23/48

CPC classification number: H05K3/3436 ,  H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/13113 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/27438 ,  H01L2224/29011 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1579 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K3/305 ,  H05K3/3431 ,  H05K3/3452 ,  H05K3/3463 ,  Y02P70/613

Abstract: Solder interconnection for forming connections between an integrated semiconductor device and a carrier substrate is provided. Located on the carrier substrate are electrodes and located between the electrodes and integrated semiconductor device are solder connections that have a relatively low melting point such that when the device is in operation, the solder connection will liquify thereby permitting expansion compensation between the substrate and semiconductor device.

Abstract translation: 提供用于形成集成半导体器件和载体衬底之间的连接的焊接互连。 位于载体衬底上的电极位于电极之间并且集成的半导体器件是具有相对较低熔点的焊料连接，使得当器件工作时，焊料连接将液化，从而允许衬底和半导体器件之间的膨胀补偿 。

公开(公告)号：US5834832A

公开(公告)日：1998-11-10

申请号：US769799

申请日：1996-12-17

Applicant: Young Do Kweon ,  Jung Jin Kim ,  Young Jae Song ,  Young Hee Song ,  Joung Rhang Lee

Inventor： Young Do Kweon ,  Jung Jin Kim ,  Young Jae Song ,  Young Hee Song ,  Joung Rhang Lee

IPC: H01L23/12 ,  H01L23/50 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34 ,  H01L23/495 ,  H01L23/02 ,  H01L23/34

CPC classification number: H05K3/341 ,  H05K1/0231 ,  H05K1/181 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L24/73 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K2201/09772 ,  H05K2201/10689 ,  H05K2201/10969 ,  H05K2201/10992 ,  H05K2201/2036 ,  H05K3/3436 ,  Y02P70/611 ,  Y02P70/613 ,  Y10S257/924

Abstract: A packing structure for a surface mounting type semiconductor package, wherein at least one semiconductor chips are mounted on a die pad. A conductive pattern is formed on a printed circuit board which is located beneath an exposed side of a die pad of the package. A nonconductive thin film or a conductive layer is formed between the conductive pattern and the die pad. The conductive pattern is electrically connected to the die pad so that there is generated the package voltage difference therebetween, thereby reducing the electric noise of the package and facilitating high speed operation of the package without reducing a mounting density.

Abstract translation: 一种用于表面安装型半导体封装的封装结构，其中至少一个半导体芯片安装在管芯焊盘上。 导电图案形成在印刷电路板上，印刷电路板位于封装的管芯焊盘的暴露侧的下方。 在导电图案和芯片焊盘之间形成非导电薄膜或导电层。 导电图案与管芯焊盘电连接，从而在其间产生封装电压差，从而降低封装的电噪声，并且便于封装的高速运行，而不会降低安装密度。

公开(公告)号：US5821604A

公开(公告)日：1998-10-13

申请号：US613136

申请日：1996-03-08

Applicant: Hidenori Egawa

Inventor： Hidenori Egawa

IPC: H01L23/498 ,  H01L23/552 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36 ,  H05K9/00

CPC classification number: H01L23/552 ,  H01L23/49816 ,  H05K1/0218 ,  H05K3/3436 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0219 ,  H05K1/141 ,  H05K2201/10969 ,  H05K2201/10992 ,  H05K3/3431 ,  H05K3/368 ,  Y02P70/613

Abstract: A hybrid integrated circuit device is equipped with a shield structure, and the shield structure has a peripheral shield frame soldered to a peripheral shield member of a mother board so as to encircle electrodes of the hybrid integrated circuit device therewith, thereby decreasing noise due to the electromagnetic wave generated by the electrodes.

Abstract translation: 混合式集成电路装置具有屏蔽结构，并且屏蔽结构具有焊接到母板的外围屏蔽构件的外围屏蔽框架，以便环绕混合集成电路装置的电极，从而降低由于 由电极产生的电磁波。