公开(公告)号：US20110239176A1

公开(公告)日：2011-09-29

申请号：US13155204

申请日：2011-06-07

Applicant: Hideki OSAKA ,  Yutaka UEMATSU

Inventor： Hideki OSAKA ,  Yutaka UEMATSU

IPC: G06F17/50

CPC classification number: H05K3/0005 ,  H05K1/0231 ,  H05K2201/093

Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

Abstract translation: 仅通过执行电磁场分析一次形成正交阵列，并且通过使用电容器的安装位置和类型以及电容器数量作为参数来确定范围以进行电路分析次数少。 通过使用计算的电源阻抗的绝对值的结果作为指标来形成估计方程，并且通过使用估计方程来设置电容器以减少噪声。

公开(公告)号：US20110234249A1

公开(公告)日：2011-09-29

申请号：US13044717

申请日：2011-03-10

Applicant: Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

Inventor： Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

IPC: G01R31/00

CPC classification number: G01R31/2889

Abstract: An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

Abstract translation: 安装有作为测试对象的集成电路的插入器设置有用于检测与集成电路的各个端子相对应的电流的开关和探头。 然后，通过作为与集成电路的电源端子连接并断开的开关的测试基板将测试图形信号输入到集成电路。 如果集成电路正常工作，并且集成电路的所有端子的电流值都在容差内，则连接到关断开关的电源端子被识别为可以被去除的端子。

公开(公告)号：US07939907B2

公开(公告)日：2011-05-10

申请号：US11755045

申请日：2007-05-30

Applicant: Hideki Osaka ,  Yutaka Uematsu ,  Eiichi Suzuki

Inventor： Hideki Osaka ,  Yutaka Uematsu ,  Eiichi Suzuki

IPC: H01L29/00 ,  H01L23/52

CPC classification number: H05K1/0236 ,  H01L23/66 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/09972 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: High density mounting and power source sharing are achieved by a digital semiconductor element and an analog semiconductor element provided in a common semiconductor device. A power layer for analog operation is connected to one end of an EBG (Electromagnetic Band Gap) layer, a power layer for digital operation is connected to the other end of the EBG layer, ground terminals for the respective elements are connected to a common ground layer, and a ground layer for separating the power layer for analog operation and the EBG layer from each other is disposed between the power layer for analog operation and the EBG layer. Thereby, high density mounting is achieved along with reducing interference of the power source to an analog chip.

Abstract translation: 通过设置在公共半导体器件中的数字半导体元件和模拟半导体元件来实现高密度安装和电源共享。 用于模拟操作的功率层连接到EBG（电磁带隙）层的一端，用于数字操作的功率层连接到EBG层的另一端，各个元件的接地端子连接到公共地 层和用于模拟操作的功率层和EBG层之间分离的接地层设置在用于模拟操作的功率层和EBG层之间。 从而，实现了高密度安装，同时减少了电源对模拟芯片的干扰。

公开(公告)号：US07768867B2

公开(公告)日：2010-08-03

申请号：US11761470

申请日：2007-06-12

Applicant: Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

Inventor： Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

IPC: G11C8/00

CPC classification number: G11C7/02 ,  G11C5/02 ,  G11C5/04 ,  H01L25/105 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

Abstract: Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.

Abstract translation: 叠层半导体器件包括多个存储器芯片，堆叠在一起，其中高速传输中的波形失真被去除。 堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。 作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。 数据选通信号和反相数据选通信号相互配合。 用于数据选通信号L4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于/ DQS信号L5的反相数据选通信号线连接到第二存储芯片11的反相数据选通信号（/ DQS）焊盘 存储芯片12。

公开(公告)号：US20090245424A1

公开(公告)日：2009-10-01

申请号：US12481798

申请日：2009-06-10

Applicant: Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

Inventor： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

IPC: H03K9/00

CPC classification number: H03K5/082 ,  H03K5/135

Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

Abstract translation: 本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。 本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。 由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收机接收到的数据的状态，并根据保持的状态和输入来调整提取输入数据的定时 数据。 作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。 接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

公开(公告)号：US07558336B2

公开(公告)日：2009-07-07

申请号：US10982946

申请日：2004-11-08

Applicant: Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

Inventor： Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba ,  Kazuyoshi Shoji

IPC: H03K9/00 ,  H04B3/46 ,  G06K5/04 ,  H03M13/00 ,  G06F13/42

CPC classification number: H03K5/082 ,  H03K5/135

Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

Abstract translation: 本发明的一个目的是通过接口接收机减少取决于数据模式的抖动。 本发明的另一个目的是提供一种LSI能够自动调整抖动减少的延迟时间，以便能够控制每个设备的设置。 由于根据数据模式的抖动可以根据先前状态如何被预期，所以保持由接收器接收到的数据的状态，并且根据保持的状态和输入来调整提取输入数据的定时 数据。 作为位于接收机中的控制机构，为了确定取决于安装形式的延迟时间，驱动器以一个周期的间隔发送和接收设置的脉冲数据，并以两个周期的间隔设置脉冲数据作为测试模式。 接收机具有自动控制机构，用于根据脉冲宽度不同的脉冲的上升时间与其下降时间之间的差来确定对系统最佳的延迟时间。

公开(公告)号：US07515157B2

公开(公告)日：2009-04-07

申请号：US10333132

申请日：2000-12-14

Applicant: Toyohiko Komatsu ,  Hideki Osaka ,  Masashi Horiguchi ,  Susumu Hatano ,  Kazuya Ito

Inventor： Toyohiko Komatsu ,  Hideki Osaka ,  Masashi Horiguchi ,  Susumu Hatano ,  Kazuya Ito

IPC: G06F13/14

CPC classification number: H04L12/40

Abstract: A data transfer method is executed to transit a three-state transmitting circuit from a high-impedance state into a data output state, transmit a preamble (dummy data) onto a bus, and sequentially transmit the essential data. The shortening of a waveform caused in the first data piece after the transition from the high-impedance state into the data output state is executed against the preamble and no shortening of a waveform is not brought about in the essential data subsequent to the preamble. This makes it possible to exclude the limitation on speeding up the data transfer imposed by the shortening of the waveform.

Abstract translation: 执行数据传送方法以将三状态发送电路从高阻抗状态转移到数据输出状态，将前导码（虚拟数据）发送到总线上，并且顺序发送基本数据。 在从高阻抗状态转换到数据输出状态之后，在第一数据段中引起的波形的缩短针对前同步码执行，并且在前导码之后的基本数据中不会引起波形的缩短。 这使得可以排除由于缩短波形而加速数据传输的限制。

公开(公告)号：US07505285B2

公开(公告)日：2009-03-17

申请号：US11404912

申请日：2006-04-17

Applicant: Hideki Osaka

Inventor： Hideki Osaka

IPC: H01R12/16

CPC classification number: H05K1/0236 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/167 ,  H05K2201/044 ,  H05K2201/09681 ,  H05K2201/0969

Abstract: A motherboard for backplane buses is provided that reduces noise due to entry of external signals into signal wiring which interconnects modules, or noise due to any external signals entering a power supply after being routed around the power supply.An EBG pattern formed up of two wiring regions different from each other in impedance is periodically disposed in at least three arrays as part of the power supply layer(s) constituting a microstripline structure (one layer adjacent to a signal layer is a power supply layer, and the other layer is interposed in air) or a stripline structure (both layers adjacent to a signal layer are power supply layers); the part of the power supply layer(s) not being involved in signal transmission between the modules on the motherboard for backplane buses.

Abstract translation: 提供了用于背板总线的主板，其将由于外部信号进入到互连模块的信号布线而引起的噪声，或者由于任何外部信号在绕过电源而进入电源之后产生的噪声。 由构成微带结构的电源层的一部分（至少与信号层相邻的一层是供电层），在至少三个阵列中周期性地设置由阻抗彼此不同的两个布线区域形成的EBG图案 ，另一层插入空气）或带状线结构（与信号层相邻的两层是电源层）; 电源层的一部分不涉及用于背板总线的主板上的模块之间的信号传输。

公开(公告)号：US20080290495A1

公开(公告)日：2008-11-27

申请号：US12068606

申请日：2008-02-08

Applicant: Yutaka Uematsu ,  Tatsuya Saito ,  Hideki Osaka ,  Yoji Nishio ,  Shunichi Saito

Inventor： Yutaka Uematsu ,  Tatsuya Saito ,  Hideki Osaka ,  Yoji Nishio ,  Shunichi Saito

IPC: H01L23/528

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/09 ,  H05K1/111 ,  H05K1/167 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09781 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.

Abstract translation: 作为半导体芯片中的馈电路径，可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径，从而抑制半导体器件的功率噪声。 通过插入将中频带中的电阻提升到电阻本身较高的部分的结构，例如半导体封装中的功率布线和电容器互连电极部件，可以有效地减少中频带中的反谐振阻抗，同时保持 阻抗低在低频。

公开(公告)号：US07447708B2

公开(公告)日：2008-11-04

申请号：US11054387

申请日：2005-02-10

Applicant: Ryuichi Hattori ,  Toshihiko Ogura ,  Takashi Oeda ,  Koichi Okazawa ,  Hideki Osaka ,  Tsunehiro Tobita ,  Tsutomu Hara

Inventor： Ryuichi Hattori ,  Toshihiko Ogura ,  Takashi Oeda ,  Koichi Okazawa ,  Hideki Osaka ,  Tsunehiro Tobita ,  Tsutomu Hara

IPC: G06F17/30 ,  G06F15/16

CPC classification number: G06F9/5055 ,  G06F9/5044 ,  G06F2209/5015 ,  H04L29/12047 ,  H04L41/5009 ,  H04L61/15 ,  H04L67/36

Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

Abstract translation: 在通过网络彼此连接的每个信息处理设备中，布置了其功能和性能被注册到其中的服务质量（QOS）表。 当信息处理设备另外与网络链接时，其QOS表被自动地注册到网络的本地目录，使得代理将QOS表的内容转换成要经由用户界面提供给用户的服务信息 。 由于操作，连接到网络的每个信息处理设备的功能和性能的信息被转换成用户的服务信息。 因此，用户可以更多地直接接收必要的服务。