公开(公告)号：US20190042968A1

公开(公告)日：2019-02-07

申请号：US16013384

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Lester Lampert ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  James S. Clarke

IPC: G06N99/00 ,  B82Y10/00 ,  H01L27/18 ,  H01L39/22 ,  H03K19/195

Abstract: Embodiments of the present disclosure describe quantum circuit assemblies utilizing triaxial cables to communicate signals to/from quantum circuit components. One assembly includes a cooling apparatus for cooling a quantum circuit component that includes at least one qubit device. The cooling apparatus includes at least one triaxial connector for providing signals to and/or receiving signals from the quantum circuit component using one or more triaxial cables. Other assemblies include quantum circuit components and various electronic components (e.g. attenuators, filters, or amplifiers) for use within the cooling apparatus, adapted to be used with triaxial cables by incorporating triaxial connectors as well.

公开(公告)号：US20190042967A1

公开(公告)日：2019-02-07

申请号：US16011812

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Zachary R. Yoscovits ,  Roman Caudillo ,  Ravi Pillarisetty ,  Hubert C. George ,  Adel A. Elsherbini ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts

IPC: G06N99/00 ,  H03K19/195 ,  H03K17/92 ,  H01L27/18 ,  B82Y10/00

CPC classification number: G06N10/00 ,  B82Y10/00 ,  G11C11/44 ,  H01L27/18 ,  H01L29/66439 ,  H01L29/66977 ,  H01L39/223 ,  H01L39/2493 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H03K17/92 ,  H03K19/1952

Abstract: Disclosed herein are superconducting qubit devices with Josephson Junctions utilizing resistive switching materials, i.e., resistive Josephson Junctions (RJJs), as well as related methods and quantum circuit assemblies. In some embodiments, an RJJ may include a bottom electrode, a top electrode, and a resistive switching layer (RSL) disposed between the bottom electrode and the top electrode. Using the RSLs in Josephson Junctions of superconducting qubits may allow fine tuning of junction resistance, which is particularly advantageous for optimizing performance of superconducting qubit devices. In addition, RJJs may be fabricated using methods that could be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to approaches for forming conventional Josephson Junctions, such as e.g. double-angle shadow evaporation approach.

公开(公告)号：US10186582B2

公开(公告)日：2019-01-22

申请号：US15123242

申请日：2014-06-13

Applicant: Intel Corporation

Inventor： Roman Caudillo ,  Uygar Avci

IPC: H01L29/16 ,  H01L21/02 ,  H01L23/29 ,  B82Y25/00 ,  H01L21/04 ,  H01L23/532 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  B82Y30/00

Abstract: Embodiments of the present disclosure describe multi-layer graphene assemblies including a layer of fluorinated graphene, dies and systems containing such structures, as well as methods of fabrication. The fluorinated graphene provides an insulating interface to other graphene layers while maintaining the desirable characteristics of the nonfluorinated graphene layers. The assemblies provide new options for utilizing graphene in integrated circuit devices and interfacing graphene with other materials. Other embodiments may be described and/or claimed.

公开(公告)号：US12230687B2

公开(公告)日：2025-02-18

申请号：US17117337

申请日：2020-12-10

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Stephanie A. Bojarski ,  Hubert C. George ,  Payam Amin ,  Patrick H. Keys ,  Ravi Pillarisetty ,  Roman Caudillo ,  Florian Luethi ,  James S. Clarke

IPC: H01L29/49 ,  B82Y10/00 ,  B82Y30/00 ,  G06N10/00 ,  H01L29/06 ,  H01L29/15 ,  H01L29/423

Abstract: Disclosed herein are lateral gate material arrangements for quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; and a gate above the quantum well stack, wherein the gate includes a gate electrode, the gate electrode includes a first material proximate to side faces of the gate and a second material proximate to a center of the gate, and the first material has a different material composition than the second material.

公开(公告)号：US11901404B2

公开(公告)日：2024-02-13

申请号：US17578043

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Manish Chandhok ,  Abhishek A. Sharma ,  Roman Caudillo ,  Scott B. Clendenning ,  Cheyun Lin

IPC: H01L21/00 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L28/87 ,  H10B12/033 ,  H10B12/31

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11791375B2

公开(公告)日：2023-10-17

申请号：US17578839

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Sudipto Naskar ,  Manish Chandhok ,  Abhishek A. Sharma ,  Roman Caudillo ,  Scott B. Clendenning ,  Cheyun Lin

IPC: H01L21/00 ,  H01L49/02 ,  H10B12/00

CPC classification number: H01L28/87 ,  H10B12/033 ,  H10B12/31

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11677017B2

公开(公告)日：2023-06-13

申请号：US17472015

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Van H. Le ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  Payam Amin ,  Zachary R. Yoscovits ,  Roman Caudillo ,  James S. Clarke ,  Roza Kotlyar ,  Kanwaljit Singh

IPC: H01L29/66 ,  G06N10/00 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L29/15 ,  H01L29/78 ,  H01L29/82 ,  H01L29/43

CPC classification number: H01L29/66977 ,  G06N10/00 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/158 ,  H01L29/66984 ,  H01L29/7831 ,  H01L29/82 ,  H01L29/437

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

公开(公告)号：US11658212B2

公开(公告)日：2023-05-23

申请号：US16274572

申请日：2019-02-13

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Stephanie A. Bojarski ,  Roman Caudillo ,  David J. Michalak ,  Jeanette M. Roberts ,  Thomas Francis Watson

IPC: H01L29/12 ,  H01L29/16 ,  G06N10/00 ,  H01L29/78 ,  H01L23/522

CPC classification number: H01L29/122 ,  G06N10/00 ,  H01L29/16 ,  H01L29/7851 ,  H01L23/5226

Abstract: Disclosed herein are quantum dot devices with conductive liners, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base, a first fin extending from the base, a second fin extending from the base, a conductive material between the first fin and the second fin, and a dielectric material between the conductive material and the first fin.

公开(公告)号：US11557630B2

公开(公告)日：2023-01-17

申请号：US16643322

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Nicole K. Thomas ,  Abhishek A. Sharma ,  Hubert C. George ,  Jeanette M. Roberts ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Kanwaljit Singh ,  James S. Clarke

IPC: H01L27/24 ,  H01L45/00 ,  G06N10/00 ,  H01L29/12 ,  H01L29/15 ,  H01L29/43 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423

Abstract: Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of selectors above the array of quantum dot gate electrodes. The array of quantum dot gate electrodes and the array of selectors may each be arranged in a grid.

公开(公告)号：US11482614B2

公开(公告)日：2022-10-25

申请号：US16645962

申请日：2017-12-23

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Willy Rachmady ,  Kanwaljit Singh ,  Nicole K. Thomas ,  Hubert C. George ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Payam Amin ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/66 ,  G06N10/00 ,  H01L27/088 ,  H01L29/12 ,  H01L29/165 ,  H01L29/423 ,  H01L29/43 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include a quantum well stack, the quantum well stack includes a quantum well layer, the quantum processing device further includes a plurality of gates above the quantum well stack to control quantum dot formation in the quantum well stack, and (1) gate metal of individual gates of the array of gates is tapered so as to narrow farther from the quantum well stack or (2) top surfaces of gate metal of individual gates of the array of gates are dished.