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公开(公告)号：US11810631B2
公开(公告)日：2023-11-07
申请号：US17123993
申请日：2020-12-16
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Michael Sheperek , Christopher M. Smitchger
CPC classification number: G11C29/021 , G11C29/12005 , G11C29/44 , G11C29/50004 , G11C2207/2254
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric of a memory page; responsive to the data state metric satisfying a first threshold criterion, determining a value of a voltage distribution metric associated with the page; and responsive to the voltage distribution metric value satisfying a second threshold criterion, performing a media management operation with respect to a block associated with the page.
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公开(公告)号：US11810627B2
公开(公告)日：2023-11-07
申请号：US17886884
申请日：2022-08-12
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Harish R. Singidi , Renato C. Padilla , Vamsi Pavan Rayaprolu , Ashutosh Malshe , Sampath K. Ratnam
CPC classification number: G11C16/3431 , G06F11/076 , G06F11/3037 , G11C16/08 , G11C16/349 , G11C16/3427
Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.
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公开(公告)号：US11740957B2
公开(公告)日：2023-08-29
申请号：US17506505
申请日：2021-10-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vamsi Pavan Rayaprolu , Harish R. Singidi , Kishore Kumar Muchherla , Ashutosh Malshe , Xiangang Luo
IPC: G06F11/07
CPC classification number: G06F11/0793 , G06F11/0727 , G06F11/0751
Abstract: A failure of a first memory access operation is detected at a memory device. Responsive to the detection, a first error control operation and a second error control operation are performed. In response to a determination that the second error control operation has remedied the failed first memory access operation, the second error control operation is associated with a second priority which is higher than a first priority associated with the first error control operation.
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64.发明公开公开(公告)号：US20230267968A1
公开(公告)日：2023-08-24
申请号：US17675592
申请日：2022-02-18
Applicant: Micron Technology, Inc.
Inventor： Patrick R. Khayat , Steven Michael Kientz , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Vamsi Pavan Rayaprolu
Abstract: A processing device in a memory sub-system monitors a temperature associated with a block of a memory device, the block comprising a plurality of wordlines. The processing device further determines a first amount of time between when memory cells associated with a first wordline of the plurality of wordlines of the block were written and when memory cells associated with a last wordline of the plurality of wordlines of the block were written. That first amount of time is normalized according to the temperature associated with the block. The processing device further determines, based at last in part on the first amount of time and on an associated scaling factor, an estimate of when the block will reach a uniform charge loss state.
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公开(公告)号：US11721409B2
公开(公告)日：2023-08-08
申请号：US17877810
申请日：2022-07-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vamsi Pavan Rayaprolu , Shane Nowell , Michael Sheperek , Steven Michael Kientz
CPC classification number: G11C29/44 , G11C16/349 , G11C29/10 , G11C29/12015 , G11C29/42 , G11C2207/2254
Abstract: A system can include a memory device and a processing device to perform operations that include determining a calibration scan frequency based on an amount of elapsed time since a previous write operation performed on the memory device, determining, based on the calibration scan frequency, whether one or more scan criteria are satisfied, responsive to determining that the one or more scan criteria are satisfied, identifying one or more block families, and calibrating one or more bin pointers of each of the identified block families, wherein the calibrating comprises: for each of the identified block families, updating each of the one or more bin pointers of the identified block family based on a data state metric of at least one block of the identified block family.
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Patent Agency Ranking
公开(公告)号：US11720286B2
公开(公告)日：2023-08-08
申请号：US17516009
申请日：2021-11-01
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Kishore Kumar Muchherla , Shane Nowell , Peter Feeley , Qisong Lin
CPC classification number: G06F3/0659 , G06F3/0619 , G06F3/0653 , G06F3/0679
Abstract: An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.
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公开(公告)号：US11715541B2
公开(公告)日：2023-08-01
申请号：US17867538
申请日：2022-07-18
Applicant: Micron Technology, Inc.
Inventor： Renato C. Padilla , Sampath K. Ratnam , Christopher M. Smitchger , Vamsi Pavan Rayaprolu , Gary F. Besinga , Michael G. Miller , Tawalin Opastrakoon
CPC classification number: G11C29/10 , G06F11/076 , G06F11/0736 , G06F11/0757 , G06F11/1048 , G11C29/52
Abstract: A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.
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公开(公告)号：US20230205442A1
公开(公告)日：2023-06-29
申请号：US18118082
申请日：2023-03-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shane Nowell , Michael Sheperek , Larry J. Koudele , Vamsi Pavan Rayaprolu
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0629 , G06F3/0679 , G06F3/0653 , G06F3/0619 , G06F3/0659
Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.
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公开(公告)号：US20230153011A1
公开(公告)日：2023-05-18
申请号：US18098279
申请日：2023-01-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Harish R Singidi , Ashutosh Malshe , Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla
CPC classification number: G06F3/0652 , G06F3/0608 , H03M7/6011 , G06F11/1004 , G06F3/0679
Abstract: A processing device, operatively coupled with a memory device, is configured to perform a write operation on a page of a plurality of pages of a data unit of a memory device. The processing device further generates a parity page for data stored in the page of the data unit and associates the parity page with parity data associated with the data unit. Responsive to determining that a first size of the parity data is larger than a first threshold size, the processing device compresses the parity data. Responsive to determining that a second size of the compressed parity data is larger than a second threshold size, the processing device releases at least a subset of the parity data corresponding to a subset of the data that is free from defects.
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70.发明公开公开(公告)号：US20230141893A1
公开(公告)日：2023-05-11
申请号：US18093646
申请日：2023-01-05
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Vamsi Pavan Rayaprolu , Larry J. Koudele
CPC classification number: G11C16/3459 , G11C16/3404 , G11C7/04 , G11C16/10 , G11C16/32 , G11C16/26
Abstract: A memory sub-system to receive a request to execute a read operation associated with data of a memory unit of a memory sub-system. A time after program associated with the data is determined. A temperature level associated with the memory unit is determined. Based on the time after program and the temperature level, a set of read offset values to apply in executing the read operation is determined. The read operation is executed using the set of read offset values.
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