中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

275 records (took 0.027 seconds)

    MACHINE LEARNING-BASED ADJUSTMENT OF MEMORY CONFIGURATION PARAMETERS
    61.
    发明公开
    MACHINE LEARNING-BASED ADJUSTMENT OF MEMORY CONFIGURATION PARAMETERS 审中-公开

    公开(公告)号：US20240330717A1

    公开(公告)日：2024-10-03

    申请号：US18597851

    申请日：2024-03-06

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Wei Wang ,  Zhenming Zhou

    IPC: G06N5/022 ,  G06F12/02

    CPC classification number: G06N5/022 ,  G06F12/0246

    Abstract: A method for using and system for training a trainable model to predict values of memory configuration parameters based on a value of a performance metric. The value of the performance metric is based on a threshold condition of a memory access operation performed on a memory device using a set of values of the memory configuration parameters. The output of the trainable model includes a set of predicted values of the memory configuration parameters. Responsive to determining that the set of predicted values of the memory configuration parameters satisfies a confidence criterion, the memory configuration parameters are updated to reflect the set of predicted values of the memory configuration parameters.

    PARTIALLY GOOD BLOCK HANDLING IN A MEMORY DEVICE
    62.
    发明公开
    PARTIALLY GOOD BLOCK HANDLING IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240330094A1

    公开(公告)日：2024-10-03

    申请号：US18618639

    申请日：2024-03-27

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Jiangli Zhu ,  Zhenming Zhou

    IPC: G06F11/07

    CPC classification number: G06F11/0775 ,  G06F11/0727

    Abstract: A programming failure is detected at a block of a memory device. Based on detecting the programming failure, the block is determined to be partially good based on a number of failed bytes in the block. An unfailing portion of the block is identified in response to determining the block is partially good. A record indicating the block is partially good and identifying the unfailing portion of the block is stored.

    Adaptive wear leveling for endurance compensation
    64.
    发明授权
    Adaptive wear leveling for endurance compensation 有权

    公开(公告)号：US12026042B2

    公开(公告)日：2024-07-02

    申请号：US17858731

    申请日：2022-07-06

    Applicant: Micron Technology, Inc.

    Inventor： Charles See Yeung Kwong ,  Seungjune Jeon ,  Wei Wang ,  Zhenming Zhou

    IPC: G06F11/00 ,  G06F11/07

    CPC classification number: G06F11/076 ,  G06F11/008 ,  G06F11/073 ,  G06F2201/81 ,  G06F2212/7211

    Abstract: A set of blocks of a memory device comprising a plurality of dies is identified. A block within the set of blocks is identified. The identified block is associated with a capability metric that reflects a projected reliability of the die on which the block resides. Responsive to determining that the capability metric satisfies a condition, a cycle threshold associated with the die is identified. Responsive to determining that a cycle count value derived from a program/erase cycle counter associated with the die matches the cycle threshold, the set of blocks is updated by excluding the block from the set of blocks. A program operation is performed with respect to the updated set of blocks.

    BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK
    65.
    发明公开
    BITLINE VOLTAGE ADJUSTMENT FOR PROGRAM OPERATION IN A MEMORY DEVICE WITH A DEFECTIVE DECK 审中-公开

    公开(公告)号：US20240185935A1

    公开(公告)日：2024-06-06

    申请号：US18524712

    申请日：2023-11-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yu-Chung Lien ,  Zhenming Zhou

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

    CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26

    Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a program operation on a set of cells in a block of the memory device, the block comprising a plurality of decks; determining whether at least one second deck of the plurality of decks is physically disposed below at least one first deck of the plurality of decks, wherein the at least one first deck satisfies a criterion pertaining to a functionality of a deck, and the at least one second deck of the plurality of decks does not satisfy the criterion; and responsive to determining that the at least one second deck is physically disposed below the at least one first deck, performing the program operation on the set of cells in the block using a first bitline voltage applied during a program verify phase, wherein the first bitline voltage is higher than a default program verify bitline voltage.

    READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME
    66.
    发明公开
    READ OPERATION WITH CAPACITY USAGE DETECTION SCHEME 审中-公开

    公开(公告)号：US20240177781A1

    公开(公告)日：2024-05-30

    申请号：US18388506

    申请日：2023-11-09

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Jun Wan ,  Zhenming Zhou

    IPC: G11C16/28 ,  G11C16/08 ,  G11C16/24

    CPC classification number: G11C16/28 ,  G11C16/08 ,  G11C16/24

    Abstract: A method for partial block read compensation can include receiving a read request that specifies a memory cell connected to a string of series-connected memory cells in an array of memory cells on a memory device, the string located at an intersection of a wordline and a bitline, and causing a first voltage applied to the wordline to which the specified memory cell is connected to ramp to a first predetermined value. The method can include causing a second voltage applied to the bitline to which the specified memory cell is connected to ramp to a second predetermined value, and can include comparing, using a current comparator, a current along the string with a reference current to generate an analog output signal. It can also include causing a voltage offset, based on the analog output signal, to be applied to a read voltage level during a sensing operation.

    Memory read operation using a voltage pattern based on a read command type
    67.
    发明授权
    Memory read operation using a voltage pattern based on a read command type 有权

    公开(公告)号：US11972122B2

    公开(公告)日：2024-04-30

    申请号：US17817465

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Yu-Chung Lien ,  Ching-Huang Lu ,  Zhenming Zhou

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

    Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

    ADAPTIVE INTEGRITY SCAN IN A MEMORY SUB-SYSTEM
    70.
    发明公开
    ADAPTIVE INTEGRITY SCAN IN A MEMORY SUB-SYSTEM 审中-公开

    公开(公告)号：US20240062834A1

    公开(公告)日：2024-02-22

    申请号：US17891852

    申请日：2022-08-19

    Applicant: Micron Technology, Inc.

    Inventor： Li-Te Chang ,  Murong Lang ,  Zhenming Zhou

    IPC: G06F3/06

    CPC classification number: G06F3/061 ,  G06F3/0679 ,  G06F3/0629

    Abstract: A processing device in a memory sub-system detects an occurrence of a data integrity check trigger event in the memory sub-system, and in response, identifies a memory die of a plurality of memory dies in the memory sub-system. The processing device further determines a read margin associated with a first distribution of memory cells of the identified memory die, and determines an adaptive scan frequency for the identified memory die based on the read margin associated with the first distribution of memory cells.

Patent Agency Ranking