公开(公告)号：US20210167198A1

公开(公告)日：2021-06-03

申请号：US16726263

申请日：2019-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/06 ,  H01L29/34 ,  H01L21/265 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66

Abstract: A mesa structure includes a substrate. A mesa protrudes out of the substrate. The mesa includes a slope and a top surface. The slope surrounds the top surface. A lattice damage area is disposed at inner side of the slope. The mesa can optionally further includes an insulating layer covering the lattice damage area. The insulating layer includes an oxide layer or a nitride layer.

公开(公告)号：US20210143257A1

公开(公告)日：2021-05-13

申请号：US16691616

申请日：2019-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423

Abstract: A high-electron mobility transistor includes a substrate; a buffer layer over the substrate; a GaN channel layer over the buffer layer; a AlGaN layer over the GaN channel layer; a gate recess in the AlGaN layer; a source region and a drain region on opposite sides of the gate recess; a GaN source layer and a GaN drain layer grown on the AlGaN layer within the source region and the drain region, respectively; and a p-GaN gate layer in and on the gate recess.

公开(公告)号：US11004952B1

公开(公告)日：2021-05-11

申请号：US16699706

申请日：2019-12-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Shin-Chuan Huang ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/02 ,  H01L29/40 ,  H01L29/20

Abstract: A high-electron mobility transistor includes a substrate; a buffer layer on the substrate; a AlGaN layer on the buffer layer; a passivation layer on the AlGaN layer; a source region and a drain region on the AlGaN layer; a source layer and a drain layer on the AlGaN layer within the source region and the drain region, respectively; a gate on the AlGaN layer between the source region and a drain region; and a field plate on the gate and the passivation layer. The field plate includes an extension portion that laterally extends to an area between the gate and the drain region. The extension portion has a wave-shaped bottom surface.

公开(公告)号：US20210098601A1

公开(公告)日：2021-04-01

申请号：US16666430

申请日：2019-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou ,  Chih-Tung Yeh

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/308

Abstract: According to an embodiment of the present invention, a method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

公开(公告)号：US20210013334A1

公开(公告)日：2021-01-14

申请号：US16533812

申请日：2019-08-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L21/265

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

公开(公告)号：US20170328949A1

公开(公告)日：2017-11-16

申请号：US15151748

申请日：2016-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Kuo Wang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: G01R31/28 ,  H01L23/522 ,  H01L21/66 ,  H01L23/528

CPC classification number: G01R31/2884 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/528

Abstract: A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. The first conductive component has an axis along an extending direction of the first conductive component. The via connects the first conductive component to the second conductive component. The via has a center defining a shift distance from the axis of the first conductive component. The shift distances of the via chains are different. A testing method using such a semiconductor structure includes drawing a resistance-shift distance diagram illustrating a relationship between the resistances of the via chains and the shift distances of the via chains. At least one dimensional feature is obtained from the resistance-shift distance diagram.

公开(公告)号：US20160334456A1

公开(公告)日：2016-11-17

申请号：US14708300

申请日：2015-05-11

Applicant: United Microelectronics Corp.

Inventor： Ya-Ching Cheng ,  Chun-Liang Hou ,  Hsiao-Kwang Yang ,  Chien-Jung Su ,  Guan-Lin Chen

IPC: G01R31/26 ,  G11C29/08

CPC classification number: G01R31/2831 ,  G11C29/006 ,  G11C29/08 ,  G11C29/44 ,  G11C29/50 ,  G11C29/56008

Abstract: The fail bit count data, shmoo data, static noise margins and write margins corresponding to a wafer are measured. Using the above mentioned measurements, variables used to generate the curve are calculated. The variables used to generate the curve include the standard deviation of the fail bit count data, the static noise margins and the write margins. The curve is used to determine optimal operating condition of a fabrication process.

Abstract translation: 测量对应于晶片的故障位计数数据，shmoo数据，静态噪声余量和写入裕度。 使用上述测量，计算用于生成曲线的变量。 用于生成曲线的变量包括故障位计数数据的标准偏差，静态噪声容限和写入余量。 该曲线用于确定制造过程的最佳操作条件。

公开(公告)号：US09063193B2

公开(公告)日：2015-06-23

申请号：US13744498

申请日：2013-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Chun-Liang Hou ,  Wen-Jung Liao

IPC: G01R1/073 ,  H01L21/00 ,  G01R31/26 ,  H01L21/66

CPC classification number: G01R31/2601 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A layout structure of an electronic element including an electronic matrix, a first load and a second load is disclosed. The first load couples to a first end of the electronic matrix and includes a first testing pad and a second testing pad coupling to the first testing pad. The second load couples to a second end of the electronic matrix and includes a third testing pad and a fourth testing pad coupling to the third testing pad.

Abstract translation: 公开了包括电子矩阵，第一负载和第二负载的电子元件的布局结构。 第一负载耦合到电子矩阵的第一端，并且包括耦合到第一测试焊盘的第一测试焊盘和第二测试焊盘。 第二负载耦合到电子矩阵的第二端，并且包括耦合到第三测试焊盘的第三测试焊盘和第四测试焊盘。