公开(公告)号：US20200212290A1

公开(公告)日：2020-07-02

申请号：US16255754

申请日：2019-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L41/47 ,  H01L21/762 ,  H01L43/02 ,  H01L21/768

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US09685533B1

公开(公告)日：2017-06-20

申请号：US15049133

申请日：2016-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ming Kuo ,  Po-Jen Chuang ,  Fu-Jung Chuang ,  Tsai-Yu Wen ,  Tsuo-Wen Lu ,  Yu-Ren Wang ,  Fu-Yu Tsai

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/49 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0228 ,  H01L21/28088 ,  H01L21/31111 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device and a method for manufacturing the same are provided in the present invention. The semiconductor device includes a substrate, agate structure on the substrate and two spacers on both sidewalls of the gate structure. Each spacer comprises an inner first spacer portion made of SiCN and an outer second spacer portion made of SiOCN.

公开(公告)号：US20250142958A1

公开(公告)日：2025-05-01

申请号：US18534754

申请日：2023-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Cheng Hou ,  Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66 ,  H01L29/792

Abstract: A semiconductor structure includes a SOI substrate having a device layer and a buried oxide layer contiguous with the device layer; a transistor disposed on the device layer; a dielectric layer surrounding the transistor; an interconnect structure disposed on the dielectric layer and electrically connected to a gate of the transistor; a charge trapping layer contiguous with the buried oxide layer; a capping layer contiguous with the charge trapping layer; and a conductive via penetrating through the capping layer, the charge trapping layer, the buried oxide layer, the device layer, and the dielectric layer. The conductive via is electrically connected to the interconnect structure.

公开(公告)号：US20250140666A1

公开(公告)日：2025-05-01

申请号：US18539321

申请日：2023-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai ,  Tai-Cheng Hou

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a RDL interposer having a first surface and a second surface; fanout pads and peripheral pads on the second surface; a first semiconductor die on the first surface and electrically connected to the fanout pads; a molding compound surrounding the first semiconductor die and the first surface of the RDL interposer; through mold vias in the molding compound around the first semiconductor die; peripheral solder bumps within the through mold vias and directly disposed on the peripheral pads; through silicon via pads on the rear surface of the first semiconductor die; a second semiconductor die bonded to the through silicon via pads of the first semiconductor die and the peripheral solder bumps within the through mold vias.

公开(公告)号：US20250072075A1

公开(公告)日：2025-02-27

申请号：US18946839

申请日：2024-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/45 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: A compound semiconductor device includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a passivation layer on the barrier layer, and a contact area recessed into the passivation layer and the barrier layer. The channel layer is partially exposed at a bottom of the contact area. Abi-layer silicide film is disposed on the contact area. A copper contact is disposed on the bi-layer silicide film

公开(公告)号：US20250062222A1

公开(公告)日：2025-02-20

申请号：US18379668

申请日：2023-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Cheng Hou ,  Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L23/522 ,  H01L21/768

Abstract: The present disclosure is related to a semiconductor device and a fabricating method thereof, and the semiconductor device includes a first dielectric layer and a first conductive structure. The first dielectric layer includes a stacked structure including a low-k dielectric layer, an etching stop layer, and a carbon-rich dielectric layer between the low-k dielectric layer and the etching stop layer, wherein a carbon concentration within the carbon-rich dielectric layer is above 15%. The first conductive structure is disposed in the first dielectric layer.

公开(公告)号：US20250017022A1

公开(公告)日：2025-01-09

申请号：US18888142

申请日：2024-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-AN Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US20240243057A1

公开(公告)日：2024-07-18

申请号：US18124591

申请日：2023-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L21/76805 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/11 ,  H01L27/0805 ,  H01L2224/05026 ,  H01L2224/116 ,  H01L2924/19041 ,  H01L2924/30105

Abstract: An integrated circuit includes a substrate, an interconnection layer, an insulation layer, a metal bump structure, and a metal-insulator-metal capacitor. The interconnection layer is disposed above the substrate. The interconnection layer includes an interlayer dielectric layer and an interconnection structure disposed in the interlayer dielectric layer. The insulation layer is disposed on the interconnection layer, the metal bump structure is disposed on the insulation layer, and the metal-insulator-metal capacitor is disposed conformally on the metal bump structure and the insulation layer. A manufacturing method of the integrated circuit includes the following steps.
The interconnection layer is formed above the substrate. The insulation layer is formed on the interconnection layer, the metal bump structure is formed on the insulation layer, and the metal-insulator-metal capacitor is formed conformally on the metal bump structure and the insulation layer.

公开(公告)号：US20240081154A1

公开(公告)日：2024-03-07

申请号：US18504176

申请日：2023-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Da-Jun Lin ,  Chau-Chung Hou ,  Wei-Xin Gao

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

公开(公告)号：US20230354715A1

公开(公告)日：2023-11-02

申请号：US18215162

申请日：2023-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H10N50/10 ,  H01L21/768 ,  H01L21/762 ,  H10N50/80

CPC classification number: H10N50/10 ,  H01L21/76802 ,  H01L21/762 ,  H10N50/80 ,  H10N35/01

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.