公开(公告)号：US10338821B2

公开(公告)日：2019-07-02

申请号：US15285305

申请日：2016-10-04

Applicant: SMART Modular Technologies, Inc.

Inventor： Rajesh Ananthanarayanan ,  Jinying Shen ,  Amir Alavi

IPC: G06F3/06

Abstract: Approaches, techniques, and mechanisms are disclosed for improving the performance of memory controllers for memory devices. A system may have a memory controller that interfaces with a memory device to store or retrieve information. When the system needs to retrieve information from the memory device, the memory controller sends an address and a command to instruct the memory device to read the information stored at the address. The memory device reads the information, and after a specific amount of time, the memory device sends the information to the memory controller. According to an embodiment, “dummy” data is sent first prior to the availability of the data read out of the memory devices, while waiting for the requested data to be accessed, and then the actual data is sent immediately following the dummy data. According to an embodiment, a geometry of a memory device has only one column of memory cells that are used to store information. The memory device with only one column in an embodiment does not require decoding of a column address. As such, the read latency of the memory device is significantly reduced.

公开(公告)号：US09946469B2

公开(公告)日：2018-04-17

申请号：US15076433

申请日：2016-03-21

Applicant: SMART Modular Technologies, Inc.

Inventor： Fong-Long Lin ,  Shu-Cheng Lin

IPC: G06F11/10 ,  G06F3/06 ,  G11C16/34

CPC classification number: G06F11/1044 ,  G11C16/0483 ,  G11C16/3427

Abstract: A solid state storage system, and method of operation thereof, including: a system interface configured to receive host commands; a controller, coupled to the system interface, configured to identify frequently read data blocks from the host commands; a non-volatile memory, coupled to the controller, configured for access of the frequently read data blocks; an error correction code unit, coupled to the controller, configured to provide health monitor parameters for the frequently read data blocks verified by the controller; and a redundant frequently read data (RFRD) area, coupled to the error correction code unit, configured to transfer a recovered data from the frequently read data blocks.

公开(公告)号：US09779016B1

公开(公告)日：2017-10-03

申请号：US13940118

申请日：2013-07-11

Applicant: SMART Modular Technologies, Inc.

Inventor： Jinying Shen ,  Robert Tower Frey ,  Kelvin Marino

IPC: G06F12/00 ,  G06F12/02 ,  G06F11/14 ,  G06F1/30 ,  G06F11/07

CPC classification number: G06F12/0246 ,  G06F1/28 ,  G06F1/30 ,  G06F11/0754 ,  G06F11/1456 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/314

Abstract: An integrated circuit system, and a method of operation thereof, including: a memory unit having a volatile memory device with data and a non-volatile controller unit; a memory unit controller of the non-volatile controller unit for receiving a snoop signal for indicating an error; a non-volatile device of the memory unit for synchronously receiving data of the volatile memory device based on the snoop signal, the data autonomously copied without any intervention from outside the memory unit to prevent loss of the data; and an in-band command received by the memory unit, for autonomously restoring the data to the volatile memory device from the non-volatile device without any intervention from outside the memory unit.

公开(公告)号：US09684520B2

公开(公告)日：2017-06-20

申请号：US13277720

申请日：2011-10-20

Applicant: Robert Tower Frey ,  Joshua Harris Brooks

Inventor： Robert Tower Frey ,  Joshua Harris Brooks

IPC: G06F12/02 ,  G06F9/44 ,  G06F11/14

CPC classification number: G06F9/442 ,  G06F11/1441

Abstract: A method for operating a computing system includes: monitoring a central interface for a power event; accessing a high-speed memory for pre-shutdown data; accessing a non-volatile memory during the power event for the pre-shutdown data previously stored on the high-speed memory; selecting a multiplexer for allowing external access to the high-speed memory; and formatting the pre-shutdown data in the non-volatile memory for access through a non-disruptive interface.

公开(公告)号：US20130132639A1

公开(公告)日：2013-05-23

申请号：US13303818

申请日：2011-11-23

Applicant: Mike H. Amidi ,  Michael Rubino ,  Alessandro Fin

Inventor： Mike H. Amidi ,  Michael Rubino ,  Alessandro Fin

IPC: G06F12/00

CPC classification number: G06F12/0804 ,  G06F3/0661 ,  G06F13/16 ,  G06F2212/2022 ,  G06F2212/3042

Abstract: A method of operation of a non-volatile memory packaging system includes: addressing an integrated circuit package having a system interface; accessing a module controller, in the integrated circuit package, through system interface; accessing a random access memory, in the integrated circuit package, by the module controller for storing data from the system interface; writing to a non-volatile memory, in the integrated circuit package by the module controller, with the data from the random access memory; and monitoring an address look-up register, by the module controller, for reading the data from the non-volatile memory or the random access memory through the system interface.

Abstract translation: 非易失性存储器封装系统的操作方法包括：寻址具有系统接口的集成电路封装; 通过系统接口访问集成电路封装中的模块控制器; 通过模块控制器访问集成电路封装中的随机存取存储器，用于存储来自系统接口的数据; 在模块控制器的集成电路封装中写入来自随机存取存储器的数据的非易失性存储器; 以及由模块控制器监视地址查找寄存器，用于通过系统接口从非易失性存储器或随机存取存储器读取数据。

公开(公告)号：US20130128685A1

公开(公告)日：2013-05-23

申请号：US13303863

申请日：2011-11-23

Applicant: Jingying Shen ,  Robert Tower Frey ,  Kelvin Marino ,  Joshua Harris Brooks

Inventor： Jingying Shen ,  Robert Tower Frey ,  Kelvin Marino ,  Joshua Harris Brooks

IPC: G11C5/14 ,  G11C5/06

CPC classification number: G11C5/141 ,  Y10T29/49117

Abstract: A method of manufacture of the memory management system includes: fabricating a dual in-line memory module carrier; mounting a volatile memory device on the dual in-line memory module carrier; mounting a non-volatile memory on the dual in-line memory module carrier on a side opposite the volatile memory device; mounting an uninterruptible power supply on the dual in-line memory module carrier for maintaining a memory module power when a system power input decays; and mounting a controller logic integrated circuit on the dual in-line memory module carrier coupled to the volatile memory device, the non-volatile memory, and the uninterruptible power supply for copying data content of the volatile memory device to the non-volatile memory when the uninterruptible power supply detects the decay of the system power input to a first cross-over level.

Abstract translation: 存储器管理系统的制造方法包括：制造双列直插存储器模块载体; 在双列直插存储器模块载体上安装易失性存储器件; 在与所述易失性存储器设备相对的一侧上的所述双列直插存储器模块载体上安装非易失性存储器; 在双列直插存储器模块载体上安装不间断电源，以在系统电源输入衰减时维持存储器模块电源; 以及将控制器逻辑集成电路安装在耦合到易失性存储器设备，非易失性存储器和用于将易失性存储器件的数据内容复制到非易失性存储器的不间断电源的双列直插式存储器模块载体中， 不间断电源检测到系统电源输入衰减到第一个交叉电平。

公开(公告)号：US08250295B2

公开(公告)日：2012-08-21

申请号：US10752151

申请日：2004-01-05

Applicant: Hossein Amidi ,  Kelvin A. Marino ,  Satyadey Kolli

Inventor： Hossein Amidi ,  Kelvin A. Marino ,  Satyadey Kolli

IPC: G06F12/00

CPC classification number: G11C8/12 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

Abstract translation: 透明的四级存储器模块具有前侧和后侧。 前侧具有堆叠在第一存储器等级上的第三存储器级。 背面具有堆叠在第二存储器等级上的第四存储器级。 耦合到存储器模块的仿真器基于从存储器控制器接收的信号来激活并控制来自第一存储器级，第二存储器级，第三存储器级或第四存储器级的一个单独的存储器级。

公开(公告)号：US20120060009A1

公开(公告)日：2012-03-08

申请号：US12878008

申请日：2010-09-08

Applicant: Kelvin Marino ,  Michael Rubino ,  Mike H. Amidi

Inventor： Kelvin Marino ,  Michael Rubino ,  Mike H. Amidi

IPC: G06F12/02 ,  G06F1/30

CPC classification number: G06F11/1441

Abstract: A method for operating a dynamic back-up storage system includes: providing a high speed memory including a first rank memory device and subsequent ranks of memory devices; providing a non-volatile memory for saving data from the high speed memory; and providing a control logic unit for controlling access, of a central processing unit that executes a program, from the high speed memory including restoring the subsequent ranks of memory devices while the central processing unit is executing the program from the first rank memory device.

Abstract translation: 一种用于操作动态备份存储系统的方法包括：提供包括第一等级存储器设备和随后的存储器设备的高速存储器; 提供用于从高速存储器保存数据的非易失性存储器; 以及提供控制逻辑单元，用于控制来自所述高速存储器的执行程序的中央处理单元的访问，所述高速存储器包括当所述中央处理单元从所述第一等级存储器设备执行所述程序时恢复所述后续行列。

公开(公告)号：US20100211765A1

公开(公告)日：2010-08-19

申请号：US12770576

申请日：2010-04-29

Applicant: Mike H. Amidi ,  Satyadev Kolli

Inventor： Mike H. Amidi ,  Satyadev Kolli

IPC: G06F1/24 ,  G11C5/14

CPC classification number: G11C5/143 ,  G11C7/22 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2211/4067

Abstract: A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.

公开(公告)号：US20080022166A1

公开(公告)日：2008-01-24

申请号：US11480073

申请日：2006-06-29

Applicant: Hossein Amidi ,  Michael Rubino ,  Larry C. Alchesky

Inventor： Hossein Amidi ,  Michael Rubino ,  Larry C. Alchesky

IPC: G11C29/00

CPC classification number: G11C29/06 ,  G11C5/04 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/56 ,  G11C29/56012 ,  G11C2029/5602

Abstract: A method and system for testing memory modules is disclosed. The system includes a memory module and a connector configured to receive the module. The memory module is configured to operate in two modes: In the first operation mode the module uses a frequency between a low frequency and a high frequency. In the second operation mode, the module uses a frequency lower than the lower frequency. A control circuit is coupled to the connector. The control circuit is configured to apply a control signal to the circuit module when the circuit module is received in the connector. When the circuit module is received in the connector, the control signal is applied. This applied control signal causes the module to operate in the second operation mode.

Abstract translation: 公开了一种用于测试存储器模块的方法和系统。 该系统包括存储器模块和被配置为接收模块的连接器。 存储器模块被配置为以两种模式操作：在第一操作模式中，模块使用低频和高频之间的频率。 在第二种操作模式下，模块使用低于较低频率的频率。 控制电路耦合到连接器。 控制电路被配置为当电路模块被接收在连接器中时，向电路模块施加控制信号。 当电路模块接收在连接器中时，应用控制信号。 该应用的控制信号使得模块在第二操作模式下操作。