公开(公告)号：US20240431214A1

公开(公告)日：2024-12-26

申请号：US18224050

申请日：2023-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang

IPC: H10N50/01 ,  H01F10/32 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an inter-metal dielectric (IMD) layer on a substrate, forming a contact hole in the IMD layer, forming a barrier layer and a metal layer in the contact hole, planarizing the metal layer, forming a spin orbit torque (SOT) layer on the barrier layer and the metal layer, and then forming a magnetic tunneling junction (MTJ) on the SOT layer.

公开(公告)号：US12178136B2

公开(公告)日：2024-12-24

申请号：US18239119

申请日：2023-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Liu ,  Jia-Feng Fang ,  Chun-Hsien Lin

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.

公开(公告)号：US12176375B2

公开(公告)日：2024-12-24

申请号：US17322599

申请日：2021-05-17

Applicant: United Microelectronics Corp.

Inventor： Zhaoyao Zhan ,  Jing Feng ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching-Hwa Tey

IPC: H01L27/146

Abstract: An image sensor structure including a substrate, a nanowire structure, a first conductive line, a second conductive line, and a third conductive line is provided. The nanowire structure includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer sequentially stacked on the substrate. The first doped layer and the third doped layer have a first conductive type. The second doped layer and the fourth doped layer have a second conductive type. The first conductive line is connected to a sidewall of the second doped layer. The second conductive line is connected to a sidewall of the third doped layer. The third conductive line is connected to the fourth doped layer.

公开(公告)号：US20240421219A1

公开(公告)日：2024-12-19

申请号：US18815864

申请日：2024-08-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L21/02 ,  H01L21/308 ,  H01L29/20 ,  H01L29/66

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

公开(公告)号：US20240415024A1

公开(公告)日：2024-12-12

申请号：US18216610

申请日：2023-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang

IPC: H10N50/10 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A magnetoresistive random access memory device includes a bottom electrode, a spin orbit torque (SOT) layer, a magnetic tunneling junction (MTJ) and a top electrode. The bottom electrode includes a first layer and a second layer connected with the first layer. A material of the first layer includes Tax1Ny1, a material of the second layer includes Tax2Ny2, and the following relationships are satisfied: y2/x2>1, y1/x1≥1, and y2/x2>y1/x1. The SOT layer is disposed on the bottom electrode. The MTJ is disposed on the SOT layer. The top electrode is disposed on the MTJ.

公开(公告)号：US20240413015A1

公开(公告)日：2024-12-12

申请号：US18220803

申请日：2023-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Chien-Ting Lin ,  Ssu-I Fu ,  Chin-Hung Chen

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a low-voltage (LV) region and a medium-voltage (MV) region, forming a first metal gate on the LV region and a second metal gate on the MV region, forming a first patterned mask on the second metal gate, removing part of the first metal gate, forming a second patterned mask on the first metal gate, removing part of the second metal gate, and then forming a first hard mask on the first metal gate and a second hard mask on the second metal gate.

公开(公告)号：US20240397832A1

公开(公告)日：2024-11-28

申请号：US18791383

申请日：2024-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Jin-Yan Chiou ,  Hsiang-Wen Ke

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A magnetic random access memory (MRAM) device includes a magnetic tunneling junction (MTJ) on a substrate, a first top electrode on the MTJ, a second top electrode on and directly contacting the first top electrode, and a spacer adjacent to the MTJ. Preferably, the first top electrode includes a gradient concentration while the second top electrode includes a non-gradient concentration.

公开(公告)号：US20240397712A1

公开(公告)日：2024-11-28

申请号：US18792499

申请日：2024-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

Abstract: An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.

公开(公告)号：US20240397689A1

公开(公告)日：2024-11-28

申请号：US18337434

申请日：2023-06-20

Applicant: United Microelectronics Corp.

Inventor： Hsin-Hsien Chen ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Kuo-Hsing Lee

IPC: H10B10/00

Abstract: A static random access memory (SRAM) includes a first memory cell. The first memory cell includes: a first pull-down transistor, a first pull-up transistor, a second pull-up transistor, and a second pull-down transistor arranged on a first segment of a first fin, a first segment of a second fin, a first segment of a third fin and a first segment of a fourth fin of a substrate, respectively. The first memory cell further includes a first diode and a second diode. The first diode includes a first conductive feature in contact with a top surface and multiple upper sidewalls of a first end of the first segment of the first fin. The second diode includes a second conductive feature in contact with a top surface and multiple upper sidewalls of a second end of the first segment of the fourth fin.

公开(公告)号：US12154852B2

公开(公告)日：2024-11-26

申请号：US17670520

申请日：2022-02-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768

Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.