公开(公告)号：US08669664B2

公开(公告)日：2014-03-11

申请号：US13681065

申请日：2012-11-19

Applicant: SiTime Corporation

Inventor： Pavan Gupta ,  Aaron Partridge ,  Markus Lutz

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: B81B7/0083 ,  B81B7/007 ,  B81B7/0077 ,  B81B2201/0271 ,  B81B2207/07 ,  B81B2207/094 ,  B81C1/0023 ,  B81C1/00301 ,  B81C1/00333 ,  B81C1/00341 ,  B81C2201/016 ,  B81C2203/0118 ,  B81C2203/0154 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/498 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A stacked die package for an electromechanical resonator system includes an electromechanical resonator die bonded or fixed to a control IC die for the electromechanical resonator by, for example, a thermally and/or electrically conductive epoxy. In various embodiments, the electromechanical resonator can be a micro-electromechanical system (MEMS) resonator or a nano-electromechanical system (NEMS) resonator. Certain packaging configurations that may include the chip that contains the electromechanical resonator and the control chip include chip-on-lead (COL), chip-on-paddle (COP), and chip-on-tape (COT) packages. The stacked die package may provide small package footprint and/or low package thickness, and low thermal resistance and a robust conductive path between the dice.

Abstract translation: 用于机电谐振器系统的堆叠管芯封装包括通过例如热和/或导电环氧树脂结合或固定到用于机电谐振器的控制IC管芯的机电谐振腔。 在各种实施例中，机电谐振器可以是微机电系统（MEMS）谐振器或纳米机电系统（NEMS）谐振器。 可以包括包含机电谐振器和控制芯片的芯片的某些封装结构包括芯片引线（COL），片上芯片（COP）和芯片芯片（COT）封装。 堆叠的管芯封装可以提供小的封装封装和/或低的封装厚度，以及低的热阻和在管芯之间的坚固的导电路径。

公开(公告)号：US20130330870A1

公开(公告)日：2013-12-12

申请号：US13685684

申请日：2012-11-26

Applicant: Infineon Technologies AG

Inventor： Karlheinz Mueller ,  Robert GRUENBERGER ,  WINKLER Bernhard

IPC: B81C1/00

CPC classification number: B81C1/00246 ,  B81B2201/0271 ,  B81C2203/0742

Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.

公开(公告)号：US20130075853A1

公开(公告)日：2013-03-28

申请号：US13681065

申请日：2012-11-19

Applicant: Pavan Gupta ,  Aaron Patridge ,  Markus Lutz

Inventor： Pavan Gupta ,  Aaron Patridge ,  Markus Lutz

IPC: H01L23/498 ,  H01L23/34

CPC classification number: B81B7/0083 ,  B81B7/007 ,  B81B7/0077 ,  B81B2201/0271 ,  B81B2207/07 ,  B81B2207/094 ,  B81C1/0023 ,  B81C1/00301 ,  B81C1/00333 ,  B81C1/00341 ,  B81C2201/016 ,  B81C2203/0118 ,  B81C2203/0154 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/498 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A stacked die package for an electromechanical resonator system includes an electromechanical resonator die bonded or fixed to a control IC die for the electromechanical resonator by, for example, a thermally and/or electrically conductive epoxy. In various embodiments, the electromechanical resonator can be a micro-electromechanical system (MEMS) resonator or a nano-electromechanical system (NEMS) resonator. Certain packaging configurations that may include the chip that contains the electromechanical resonator and the control chip include chip-on-lead (COL), chip-on-paddle (COP), and chip-on-tape (COT) packages. The stacked die package may provide small package footprint and/or low package thickness, and low thermal resistance and a robust conductive path between the dice.

Abstract translation: 用于机电谐振器系统的堆叠管芯封装包括通过例如热和/或导电环氧树脂结合或固定到用于机电谐振器的控制IC管芯的机电谐振腔。 在各种实施例中，机电谐振器可以是微机电系统（MEMS）谐振器或纳米机电系统（NEMS）谐振器。 可以包括包含机电谐振器和控制芯片的芯片的某些封装结构包括芯片引线（COL），片上芯片（COP）和芯片芯片（COT）封装。 堆叠的管芯封装可以提供小的封装封装和/或低的封装厚度，以及低的热阻和在管芯之间的坚固的导电路径。

公开(公告)号：US08350346B1

公开(公告)日：2013-01-08

申请号：US13541306

申请日：2012-07-03

Applicant: Kegang Huang ,  Martin Lim ,  Steven S. Nasiri

Inventor： Kegang Huang ,  Martin Lim ,  Steven S. Nasiri

IPC: H01L29/84

CPC classification number: B81B3/0051 ,  B81B7/02 ,  B81B2201/025 ,  B81B2201/0271 ,  B81C1/00293 ,  H01L29/0657

Abstract: An integrated MEMS device comprises a wafer where the wafer contains two or more cavities of different depths. The MEMS device includes one movable structure within a first cavity of a first depth and a second movable structure within a second cavity of a second depth. The cavities are sealed to maintain different pressures for the different movable structures for optimal operation. MEMS stops can be formed in the same multiple cavity depth processing flow. The MEMS device can be integrated with a CMOS wafer.

公开(公告)号：US08330238B2

公开(公告)日：2012-12-11

申请号：US12953092

申请日：2010-11-23

Applicant: Johannes van Wingerden ,  Wim van den Einden ,  Harold H. Roosen ,  Greja Johanna Adriana Maria Verheijden ,  Gerhard Koops ,  Didem Ernur ,  Jozef Thomas Martinus van Beek

Inventor： Johannes van Wingerden ,  Wim van den Einden ,  Harold H. Roosen ,  Greja Johanna Adriana Maria Verheijden ,  Gerhard Koops ,  Didem Ernur ,  Jozef Thomas Martinus van Beek

IPC: H01L29/84

CPC classification number: B81C1/00476 ,  B81B2201/0271 ,  B81C2203/0136 ,  B81C2203/0145 ,  H03H3/0072

Abstract: A method of packaging a micro electro-mechanical structure comprises forming said structure on a substrate; depositing a sacrificial layer over said structure; patterning the sacrificial layer; depositing a SIPOS (semi-insulating polycrystalline silicon) layer over the patterned sacrificial layer; treating the SIPOS layer with an etchant to convert the SIPOS layer into a porous SIPOS layer, removing the patterned sacrificial layer through the porous layer SIPOS to form a cavity including said structure; and sealing the porous SIPOS layer. A device including such a packaged micro electro-mechanical structure is also disclosed.

Abstract translation: 包装微电子机械结构的方法包括在基底上形成所述结构; 在所述结构上沉积牺牲层; 图案化牺牲层; 在图案化的牺牲层上沉积SIPOS（半绝缘多晶硅）层; 用蚀刻剂处理SIPOS层以将SIPOS层转换成多孔SIPOS层，通过多孔层SIPOS去除图案化的牺牲层以形成包括所述结构的空腔; 并密封多孔SIPOS层。 还公开了一种包括这种封装的微机电结构的装置。

公开(公告)号：US08329053B2

公开(公告)日：2012-12-11

申请号：US12623768

申请日：2009-11-23

Applicant: David Martin ,  Joel Philliber

Inventor： David Martin ,  Joel Philliber

IPC: C03C15/00

CPC classification number: B81C1/00904 ,  B81B2201/0271 ,  H01L41/0805

Abstract: In accordance with an illustrative embodiment, a method of fabricating a transducer is described. The method comprises providing a transducer over a first surface of a substrate, wherein the substrate comprises a thickness. The method further comprises patterning a mask over a second surface. The mask comprises an opening for forming a scribe etch. The method comprises etching through the opening in the mask and into but not through the thickness of the substrate to provide the scribe etch.

Abstract translation: 根据说明性实施例，描述了一种制造换能器的方法。 该方法包括在衬底的第一表面上提供换能器，其中衬底包括厚度。 该方法还包括在第二表面上图案化掩模。 掩模包括用于形成刻划蚀刻的开口。 该方法包括通过掩模中的开口蚀刻而不是通过衬底的厚度，以提供刻划蚀刻。

公开(公告)号：US08324113B2

公开(公告)日：2012-12-04

申请号：US12545235

申请日：2009-08-21

Applicant: Takahisa Kato ,  Yasuhiro Shimada

Inventor： Takahisa Kato ,  Yasuhiro Shimada

IPC: H01L21/302

CPC classification number: B81C1/00626 ,  B81B2201/0271 ,  B81C1/00404 ,  B81C2201/0133 ,  B81C2201/0198

Abstract: A silicon processing method includes: forming a mask pattern on a principal plane of a single-crystal silicon substrate; and applying crystal anisotropic etching to the principal surface to form a structure including a (111) surface and a crystal surface equivalent thereto and having width W1 and length L1. The principal plane includes a (100) surface and a crystal surface equivalent thereto or a (110) surface and a crystal surface equivalent thereto. A determining section for determining the width W1 of the structure is formed in the mask pattern. The width of the determining section for the width W1 of the mask pattern is width W2. The width of the mask pattern other than the determining section is larger than the width W2 over a length direction of the mask pattern.

Abstract translation: 硅处理方法包括：在单晶硅衬底的主平面上形成掩模图案; 并对主表面施加结晶各向异性蚀刻，形成包括（111）表面和与其等效的晶面的结构，并具有宽度W1和长度L1。 主平面包括（100）表面和与其等效的（110）表面和与其等效的（110）表面和晶体表面。 用于确定结构的宽度W1的确定部分形成在掩模图案中。 掩模图案的宽度W1的确定部的宽度为宽度W2。 除了确定部分之外的掩模图案的宽度大于在掩模图案的长度方向上的宽度W2。

公开(公告)号：US20120286903A1

公开(公告)日：2012-11-15

申请号：US13468052

申请日：2012-05-10

Applicant: Mika Prunnila ,  Antti Jaakkola ,  Tuomas Pensala

Inventor： Mika Prunnila ,  Antti Jaakkola ,  Tuomas Pensala

IPC: H01P7/00 ,  G06F17/50

CPC classification number: B81B3/0072 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0271 ,  B81C2201/0164 ,  B81C2201/0167 ,  B81C2201/0177 ,  G06F17/5045 ,  H03H9/02448 ,  H03H9/2447 ,  H03H2009/2442

Abstract: The invention relates to a micromechanical device comprising a semiconductor element capable of deflecting or resonating and comprising at least two regions having different material properties and drive or sense means functionally coupled to said semiconductor element. According to the invention, at least one of said regions comprises one or more n-type doping agents, and the relative volumes, doping concentrations, doping agents and/or crystal orientations of the regions being configured so that the temperature sensitivities of the generalized stiffness are opposite in sign at least at one temperature for the regions, and the overall temperature drift of the generalized stiffness of the semiconductor element is 50 ppm or less on a temperature range of 100° C. The device can be a resonator. Also a method of designing the device is disclosed.

Abstract translation: 本发明涉及一种微机械装置，其包括能够偏转或谐振并且包括具有不同材料特性的至少两个区域的半导体元件和功能性耦合到所述半导体元件的驱动或感测装置。 根据本发明，所述区域中的至少一个包括一种或多种n型掺杂剂，并且所述区域的相对体积，掺杂浓度，掺杂剂和/或晶体取向被构造成使得广义刚度的温度敏感度 在区域的至少一个温度下符号相反，半导体元件的整体刚度的总体温度漂移在100℃的温度范围内为50ppm以下。该器件可以是谐振器。 还公开了一种设计该设备的方法。

公开(公告)号：US20120256519A1

公开(公告)日：2012-10-11

申请号：US13436336

申请日：2012-03-30

Applicant: Toshio Tomiyoshi ,  Kazutoshi Torashima ,  Takahiro Akiyama

Inventor： Toshio Tomiyoshi ,  Kazutoshi Torashima ,  Takahiro Akiyama

IPC: H02N11/00 ,  B05D5/12

CPC classification number: H04R1/00 ,  B06B1/0292 ,  B81B2201/0271 ,  B81B2203/04 ,  B81C1/00626 ,  H04R2201/003

Abstract: An electromechanical transducer includes a substrate, a first electrode disposed on the substrate, and a vibration film including a membrane disposed on the first electrode with a space therebetween and a second electrode disposed on the membrane so as to oppose the first electrode. The first electrode has a surface roughness value of 6 nm RMS or less.

Abstract translation: 机电换能器包括基板，设置在基板上的第一电极以及设置在第一电极上的具有间隔的膜的振动膜和设置在膜上以与第一电极相对的第二电极。 第一电极的表面粗糙度值为6nm RMS以下。

公开(公告)号：US08198690B2

公开(公告)日：2012-06-12

申请号：US12853814

申请日：2010-08-10

Applicant: Florian Schoen ,  Wolfgang Raberg ,  Bernhard Winkler ,  Werner Weber

Inventor： Florian Schoen ,  Wolfgang Raberg ,  Bernhard Winkler ,  Werner Weber

IPC: H01L29/84

CPC classification number: B81C1/00182 ,  B81B2201/0271 ,  H01L41/0933 ,  Y10S977/732

Abstract: Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a first semiconductive material and at least one trench disposed in the first semiconductive material, the at least one trench having a sidewall. An insulating material layer is disposed over an upper portion of the sidewall of the at least one trench in the first semiconductive material and over a portion of a top surface of the first semiconductive material proximate the sidewall. A second semiconductive material or a conductive material is disposed within the at least one trench and at least over the insulating material layer disposed over the portion of the top surface of the first semiconductive material proximate the sidewall.

Abstract translation: 公开了微机电系统（MEMS）装置及其制造方法。 在一个实施例中，MEMS器件包括第一半导体材料和设置在第一半导体材料中的至少一个沟槽，所述至少一个沟槽具有侧壁。 绝缘材料层设置在第一半导体材料中的至少一个沟槽的侧壁的上部上方，以及靠近侧壁的第一半导体材料的顶表面的一部分之上。 第二半导体材料或导电材料设置在至少一个沟槽内，并且至少在绝缘材料层的上方设置在靠近侧壁的第一半导体材料的顶表面的部分之上。