公开(公告)号：US09758366B2

公开(公告)日：2017-09-12

申请号：US14969329

申请日：2015-12-15

Applicant: Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: H01L21/00 ,  H01L43/14 ,  H01L43/10 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81B3/0056 ,  B81B2201/012 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/0015 ,  B81C1/00619 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/0178 ,  B81C2203/0109 ,  B81C2203/0136 ,  H01H59/0009 ,  H01H2001/0078

Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

公开(公告)号：US20160052778A1

公开(公告)日：2016-02-25

申请号：US14467521

申请日：2014-08-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Earl Vedere Atnip ,  Raul Enrique Barreto ,  Kelly J. Taylor

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00666 ,  B81B3/0072 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C1/00365 ,  B81C2201/0108 ,  B81C2201/0132 ,  B81C2201/0167 ,  B81C2201/0178

Abstract: A MEMS device is formed by forming a sacrificial layer over a substrate and forming a first metal layer over the sacrificial layer. Subsequently, the first metal layer is exposed to an oxidizing ambient which oxidizes a surface layer of the first metal layer where exposed to the oxidizing ambient, to form a native oxide layer of the first metal layer. A second metal layer is subsequently formed over the native oxide layer of the first metal layer. The sacrificial layer is subsequently removed, forming a released metal structure.

Abstract translation: 通过在衬底上形成牺牲层并在牺牲层上形成第一金属层来形成MEMS器件。 随后，将第一金属层暴露于氧化环境中，氧化暴露于氧化环境的第一金属层的表面层，以形成第一金属层的天然氧化物层。 随后在第一金属层的自然氧化物层上形成第二金属层。 随后去除牺牲层，形成释放的金属结构。

公开(公告)号：US20130230939A1

公开(公告)日：2013-09-05

申请号：US13412257

申请日：2012-03-05

Applicant: Te-Hao LEE

Inventor： Te-Hao LEE

IPC: H01L21/02

CPC classification number: B81C1/00619 ,  B81C2201/0122 ,  B81C2201/0178

Abstract: An HF vapor etch etches high aspect ratio openings to form MEMS devices and other tightly-packed semiconductor devices with 0.2 μm air gaps between structures. The HF vapor etch etches oxide plugs and gaps with void portions and oxide liner portions and further etches oxide layers that are buried beneath silicon and other structures and is ideally suited to release cantilevers and other MEMS devices. The HF vapor etches at room temperature and atmospheric pressure in one embodiment. A process sequence is provided that forms MEMS devices including cantilevers and lateral, in-plane electrodes that are stationary and vibration resistant.

Abstract translation: HF蒸汽蚀刻蚀刻高纵横比开口以形成MEMS器件和其他紧密堆积的半导体器件，其中在结构之间具有0.2μm的气隙。 HF蒸汽蚀刻蚀刻具有空隙部分和氧化物衬垫部分的氧化物塞和间隙，并进一步蚀刻氧化物层，其被埋在硅和其它结构之下，并且理想地适合于释放悬臂和其它MEMS器件。 在一个实施方案中，HF蒸气在室温和大气压下蚀刻。 提供了一种形成MEMS器件的工艺顺序，其包括静止和抗振动的悬臂和侧向平面内的电极。

公开(公告)号：US06962831B2

公开(公告)日：2005-11-08

申请号：US10342949

申请日：2003-01-15

Applicant: Khalil Najafi ,  Chunbo Zhang

Inventor： Khalil Najafi ,  Chunbo Zhang

IPC: B81C1/00 ,  H01L21/762 ,  H01L21/66

CPC classification number: F28F13/185 ,  B81B2203/033 ,  B81C1/0038 ,  B81C2201/0132 ,  B81C2201/0178 ,  F28F2260/00 ,  H01L21/76208

Abstract: A method of fabricating a thick silicon dioxide layer without the need for long deposition or oxidation and a device having such a layer are provided. Deep reactive ion etching (DRIE) is used to create high-aspect ratio openings or trenches and microstructures or silicon pillars, which are then oxidized and/or refilled with LPCVD oxide or other deposited silicon oxide films to create layers as thick as the DRIE etched depth allows. Thickness in the range of 10-100 μm have been achieved. Periodic stiffeners perpendicular to the direction of the trenches are used to provide support for the pillars during oxidation. The resulting SiO2 layer is impermeable and can sustain large pressure difference. Thermal tests show that such thick silicon dioxide diaphragms or layers can effectively thermally isolate heated structures from neighboring structures and devices within a distance of hundred of microns. Such SiO2 diaphragms or layers of thickness 50-60 μm can sustain an extrinsic shear stress up to 3-5 Mpa. These thick insulating microstructures or layers can be used in thermal, mechanical, fluidic, optical, and bio microsystems.

Abstract translation: 提供了制造厚二氧化硅层而不需要长时间沉积或氧化的方法和具有这种层的器件。 深反应离子蚀刻（DRIE）用于产生高纵横比的开口或沟槽和微结构或硅柱，然后用LPCVD氧化物或其他沉积的氧化硅膜氧化和/或再填充以产生与DRIE蚀刻的厚度相同的层 深度允许。 已达到10-100mam范围内的厚度。 垂直于沟槽方向的周期性加强筋用于在氧化过程中为支柱提供支撑。 所得的SiO 2层是不渗透的并且可以承受较大的压力差。 热测试表明，这种厚的二氧化硅隔膜或层可以有效地将加热的结构与邻近的结构和器件隔离在一百微米的距离内。 厚度为50-60μm的这种SiO 2膜或层可承受高达3-5Mpa的外在剪切应力。 这些厚的绝缘微结构或层可用于热，机械，流体，光学和生物微系统。

公开(公告)号：US06797589B2

公开(公告)日：2004-09-28

申请号：US10322990

申请日：2002-12-18

Applicant: Scott G. Adams ,  Scott A. Miller

Inventor： Scott G. Adams ,  Scott A. Miller

IPC: H01L2176

CPC classification number: H01L21/76229 ,  B81B3/0086 ,  B81B2203/033 ,  B81C1/00126 ,  B81C2201/0178 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/76208

Abstract: A method of manufacturing an insulating micro-structure by etching a plurality of trenches in a silicon substrate and filling said trenches with insulating materials. The trenches are etched and then oxidized until completely or almost completely filled with silicon dioxide. Additional insulating material is then deposited as necessary to fill any remaining trenches, thus forming the structure. When the top of the structure is metallized, the insulating structure increases voltage resistance and reduces the capacitive coupling between the metal and the silicon substrate. Part of the silicon substrate underlying the structure is optionally removed further to reduce the capacitive coupling effect. Hybrid silicon-insulator structures can be formed to gain the effect of the benefits of the structure in three-dimensional configurations, and to permit metallization of more than one side of the structure.

Abstract translation: 通过蚀刻硅衬底中的多个沟槽并用绝缘材料填充所述沟槽来制造绝缘微结构的方法。 蚀刻沟槽，然后氧化直到完全或几乎完全充满二氧化硅。 然后根据需要沉积额外的绝缘材料以填充任何剩余的沟槽，从而形成结构。 当结构的顶部被金属化时，绝缘结构增加了电阻并降低了金属和硅衬底之间的电容耦合。 可选地，进一步去除结构底层的硅衬底的一部分以降低电容耦合效应。 可以形成混合硅 - 绝缘体结构以获得三维结构中结构的益处的效果，并且允许结构多于一侧的金属化。

公开(公告)号：US20040155010A1

公开(公告)日：2004-08-12

申请号：US10474968

申请日：2004-03-31

Inventor： Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Frank Schaefer

IPC: B29D011/00

CPC classification number: B81B3/0083 ,  B81B2203/0315 ,  B81C2201/0114 ,  B81C2201/0115 ,  B81C2201/0178 ,  C25F3/12 ,  C25F3/14 ,  H01L21/306 ,  H01L21/3081

Abstract: A simple and cost-effective possibility is proposed for producing optically transparent regions (5, 6) in a silicon substrate (1), by the use of which both optically transparent regions of any thickness and optically transparent regions over a cavity in a silicon substrate are able to be implemented. For this purpose, first at least a specified region (5, 6) of the silicon substrate (1) is etched porous. Thereafter, the specified porous region (5, 6) of the silicon substrate (1) is oxidized.

Abstract translation: 提出了在硅衬底（1）中制造光学透明区域（5,6）的简单和成本有效的可能性，其中通过在硅衬底的空腔上使用任何厚度和光学透明区域的两个光学透明区域 能够实施。 为此目的，首先对硅衬底（1）的至少一个特定区域（5,6）进行多孔蚀刻。 此后，硅衬底（1）的规定的多孔区域（5,6）被氧化。

公开(公告)号：US06759734B2

公开(公告)日：2004-07-06

申请号：US10100371

申请日：2002-03-14

Applicant: John H. Jerman ,  John D. Grade

Inventor： John H. Jerman ,  John D. Grade

IPC: H01L2302

CPC classification number: B81B3/0086 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81C2201/0178

Abstract: The present invention provides a miniature device that comprises a grounded layer, an insulative layer overlying the grounded layer and a conductive layer overlying the insulative layer wherein the insulative spacing between the conductive and grounded layers is increased so as to inhibit electrical shorting between the conductive layer and grounded layers. A method of making miniature devices is also provided.

Abstract translation: 本发明提供一种微型器件，其包括接地层，覆盖接地层的绝缘层和覆盖绝缘层的导电层，其中导电层和接地层之间的绝缘间距增加，以便抑制导电层之间的电短路 和接地层。 还提供了制造微型装置的方法。

公开(公告)号：US20040021186A1

公开(公告)日：2004-02-05

申请号：US10381046

申请日：2003-03-25

Inventor： Mika Okumura ,  Makio Horikawa ,  Kiyoshi Ishibashi

IPC: H01L021/00 ,  H01L029/82 ,  H01L021/469

CPC classification number: H01L21/02255 ,  B81B2201/0235 ,  B81B2203/0307 ,  B81B2207/07 ,  B81C1/00365 ,  B81C2201/0178 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/31662

Abstract: The present invention relates to a substrate and a manufacturing method thereof as well as a thin-film structural body, and an object thereof is to provide a substrate capable of reducing a stress difference generating between an oxide film on the substrate and another film formed on the oxide film upon thermal shrinkage and also shortening the time required for film formation at the time of forming a thick oxide film, and a manufacturing method thereof as well as a thin-film structural body. In order to achieve the above object, this substrate (1) is provided with a substrate main body (31) made from silicon, and an oxide film (33) for a base formed thereon. The oxide film (33) includes a first oxide film (61) made of a thermal SiO2 film formed by thermally oxidizing silicon in the substrate main body (31), and a second oxide film (63) made of a high-temperature oxide film deposited and formed thereon.

Abstract translation: 本发明涉及一种基板及其制造方法以及薄膜结构体，其目的在于提供一种基板，其能够减小基板上的氧化物膜和形成于基板上的另一膜之间的应力差产生 热收缩时的氧化膜，缩短形成厚氧化膜时的成膜所需的时间及其制造方法以及薄膜结构体。 为了实现上述目的，该基板（1）设置有由硅制成的基板主体（31）和形成在其上的基座用氧化膜（33）。 氧化膜（33）包括由在基板主体（31）中热氧化硅而形成的热SiO2膜构成的第一氧化膜（61）和由高温氧化膜 沉积并形成在其上。

公开(公告)号：US20030124758A1

公开(公告)日：2003-07-03

申请号：US10322990

申请日：2002-12-18

Inventor： Scott G. Adams ,  Scott A. Miller

IPC: H01L021/00

CPC classification number: H01L21/76229 ,  B81B3/0086 ,  B81B2203/033 ,  B81C1/00126 ,  B81C2201/0178 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/76208

Abstract: A method of manufacturing an insulating micro-structure by etching a plurality of trenches in a silicon substrate and filling said trenches with insulating materials. The trenches are etched and then oxidized until completely or almost completely filled with silicon dioxide. Additional insulating material is then deposited as necessary to fill any remaining trenches, thus forming the structure. When the top of the structure is metallized, the insulating structure increases voltage resistance and reduces the capacitive coupling between the metal and the silicon substrate. Part of the silicon substrate underlying the structure is optionally removed further to reduce the capacitive coupling effect. Hybrid silicon-insulator structures can be formed to gain the effect of the benefits of the structure in three-dimensional configurations, and to permit metallization of more than one side of the structure.

Abstract translation: 通过蚀刻硅衬底中的多个沟槽并用绝缘材料填充所述沟槽来制造绝缘微结构的方法。 蚀刻沟槽，然后氧化直到完全或几乎完全充满二氧化硅。 然后根据需要沉积额外的绝缘材料以填充任何剩余的沟槽，从而形成结构。 当结构的顶部被金属化时，绝缘结构增加了电阻并降低了金属和硅衬底之间的电容耦合。 可选地，进一步去除结构底层的硅衬底的一部分以降低电容耦合效应。 可以形成混合硅 - 绝缘体结构以获得三维结构中结构的益处的效果，并且允许结构多于一侧的金属化。

公开(公告)号：US20030019832A1

公开(公告)日：2003-01-30

申请号：US10076296

申请日：2002-02-13

Applicant: The Regents of the University of California

Inventor： Robert A. Conant ,  Jocelyn T. Nee ,  Kam-Yin Lau ,  Richard S. Muller

IPC: C23F001/00

CPC classification number: B81C1/00182 ,  B81B2201/042 ,  B81B2203/0136 ,  B81C2201/0178 ,  B81C2203/032 ,  G02B26/0841

Abstract: A staggered torsional electrostatic combdrive includes a stationary combteeth assembly and a moving combteeth assembly with a mirror and a torsional hinge. The moving combteeth assembly is positioned entirely above the stationary combteeth assembly by a predetermined vertical displacement during a combdrive resting state. A method of fabricating the staggered torsional electrostatic combdrive includes the step of deep trench etching a stationary combteeth assembly in a first wafer. A second wafer is bonded to the first wafer to form a sandwich including the first wafer, an oxide layer, and the second wafer. A moving combteeth assembly is formed in the second wafer. The moving combteeth assembly includes a mirror and a torsional hinge. The moving combteeth assembly is separated from the first wafer by the oxide layer. The oxide layer is subsequently removed to release the staggered torsional electrostatic combdrive.

Abstract translation: 交错的扭转静电梳状驱动器包括固定的组合组件和具有反射镜和扭转铰链的移动梳状组件。 移动的组合组件在梳齿装置静止状态期间完全位于固定组合组件上方预定的垂直位移。 制造交错扭转静电梳齿驱动器的方法包括在第一晶片中深沟槽蚀刻静止梳组件的步骤。 第二晶片结合到第一晶片以形成包括第一晶片，氧化物层和第二晶片的夹层。 在第二晶片中形成移动的组合组件。 移动的组合组件包括反射镜和扭转铰链。 移动的组合组件通过氧化物层与第一晶片分离。 随后去除氧化物层以释放交错的扭转静电梳状驱动。