公开(公告)号：US08187479B2

公开(公告)日：2012-05-29

申请号：US12273961

申请日：2008-11-19

Applicant: Myung-Sam Kang

Inventor： Myung-Sam Kang

IPC: B44C1/22

CPC classification number: H05K3/421 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/427 ,  H05K3/4652 ,  H05K2201/0341 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/0361 ,  H05K2203/0384 ,  H05K2203/1388

Abstract: Disclosed is a manufacturing method of a printed circuit board. The method in accordance with an embodiment of the present invention includes: providing a laminated substrate having an insulator as well as a first metal layer and a second metal layer, which are sequentially laminated on one side of the insulator; processing a via hole in the laminated substrate; forming a seed layer on an inner wall of the via hole and on a surface of the second metal layer; plating an inside of the via hole and the surface of the second metal layer with a conductive material that is different from a material of the second metal layer; etching the seed layer and the conductive material, formed on the second metal layer; etching the second metal layer; and forming a first circuit pattern by selectively etching the first metal layer.

Abstract translation: 公开了一种印刷电路板的制造方法。 根据本发明的实施例的方法包括：提供具有绝缘体的层叠基板以及依次层压在绝缘体的一侧上的第一金属层和第二金属层; 处理层压基板中的通孔; 在所述通孔的内壁上和所述第二金属层的表面上形成种子层; 用与第二金属层的材料不同的导电材料电镀通孔内表面和第二金属层表面; 蚀刻形成在第二金属层上的种子层和导电材料; 蚀刻第二金属层; 以及通过选择性地蚀刻所述第一金属层来形成第一电路图案。

公开(公告)号：US08058568B2

公开(公告)日：2011-11-15

申请号：US12188551

申请日：2008-08-08

Applicant: Chia-Wei Chang

Inventor： Chia-Wei Chang

IPC: H05K1/11 ,  H05K1/00 ,  H05K1/09

CPC classification number: H05K3/4661 ,  H05K3/108 ,  H05K3/243 ,  H05K3/244 ,  H05K3/3452 ,  H05K3/3473 ,  H05K3/386 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0341 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2203/0353 ,  H05K2203/043 ,  H05K2203/054 ,  H05K2203/1152 ,  Y10T29/49124

Abstract: A circuit board and a method for fabricating the same are provided. The circuit board includes a core board, a first bonding layer disposed on the core board, and a first wiring layer disposed on the first bonding layer. The first bonding layer enables the first wiring layer to be bonded to the core layer better, thereby preventing delamination and forming a fine-pitch wiring layer.

Abstract translation: 提供一种电路板及其制造方法。 电路板包括芯板，设置在芯板上的第一接合层和设置在第一接合层上的第一布线层。 第一接合层能够使第一布线层更好地与芯层接合，从而防止分层并形成细间距布线层。

公开(公告)号：US20110051376A1

公开(公告)日：2011-03-03

申请号：US12941894

申请日：2010-11-08

Applicant: Daewoong Suh ,  Stephen E. Lehman, JR. ,  Mukul Renavikar

Inventor： Daewoong Suh ,  Stephen E. Lehman, JR. ,  Mukul Renavikar

IPC: H05K7/00 ,  H05K1/11

CPC classification number: H05K3/3484 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/11 ,  H01L2224/11822 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/81011 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/0215 ,  H05K2201/0341 ,  H05K2203/0435 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.

Abstract translation: 描述了一种微电子组件及其制造方法。 在一个示例中，微电子组件包括具有一个或多个区域以接收一个或多个焊球的表面的微电子器件，所述一个或多个区域具有包括Ni的表面光洁度。 将包含Cu的焊料材料（例如焊剂或糊料）施加到Ni表面光洁度上，并且一个或多个焊球通过在一个或多个焊球之间形成焊料接头的回流工艺耦合到微电子器件，焊料 包含Cu的材料，并且所述一个或多个区域具有包括Ni的表面光洁度。

公开(公告)号：US07700476B2

公开(公告)日：2010-04-20

申请号：US11602914

申请日：2006-11-20

Applicant: Daewoong Suh ,  Stephen E. Lehman, Jr. ,  Mukul Renavikar

Inventor： Daewoong Suh ,  Stephen E. Lehman, Jr. ,  Mukul Renavikar

IPC: H01L21/44

CPC classification number: H05K3/3484 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/11 ,  H01L2224/11822 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/81011 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/0215 ,  H05K2201/0341 ,  H05K2203/0435 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A microelectronic assembly and method for fabricating the same are described. In an example, a microelectronic assembly includes a microelectronic device having a surface with one or more areas to receive one or more solder balls, the one or more areas having a surface finish comprising Ni. A solder material comprising Cu, such as flux or paste, is applied to the Ni surface finish and one or more solder balls are coupled to the microelectronic device by a reflow process that forms a solder joint between the one or more solder balls, the solder material comprising Cu, and the one or more areas having a surface finish comprising Ni.

Abstract translation: 描述了一种微电子组件及其制造方法。 在一个示例中，微电子组件包括具有一个或多个区域以接收一个或多个焊球的表面的微电子器件，所述一个或多个区域具有包括Ni的表面光洁度。 将包含Cu的焊料材料（例如焊剂或糊料）施加到Ni表面光洁度上，并且一个或多个焊球通过在一个或多个焊球之间形成焊料接头的回流工艺耦合到微电子器件，焊料 包含Cu的材料，并且所述一个或多个区域具有包括Ni的表面光洁度。

公开(公告)号：US20090199399A1

公开(公告)日：2009-08-13

申请号：US12163252

申请日：2008-06-27

Applicant: Takashi Kariya ,  Toshiki Furutani

Inventor： Takashi Kariya ,  Toshiki Furutani

IPC: H05K3/30

CPC classification number: H05K3/428 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/26175 ,  H01L2224/73204 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01093 ,  H01L2924/14 ,  H05K1/187 ,  H05K3/205 ,  H05K3/243 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0959 ,  H05K2201/0969 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2203/0361 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A method for manufacturing a board with a built-in electronic element, includes providing a support substrate including a support base and a metal foil, forming a protective film made of a metal material on the metal foil of the support substrate, forming a conductive pattern made of a metal material on the protective film by an additive method, placing an electronic element on the support substrate with the conductive pattern such that a surface of the electronic element where a circuit is formed faces the conductive pattern, covering the electronic element with an insulative resin, etching away the metal foil using a first etching solution such that the protective film is not dissolved by the first etching solution or that the protective film has an etching speed which is slower than an etching speed of the metal foil, and electrically connecting terminals of the electronic element and a part of the conductive pattern.

Abstract translation: 一种用于制造具有内置电子元件的板的方法，包括提供包括支撑基底和金属箔的支撑基板，在支撑基板的金属箔上形成由金属材料制成的保护膜，形成导电图案 通过添加方法在保护膜上由金属材料制成，将电子元件放置在具有导电图案的支撑基板上，使得形成电路的电子元件的表面面向导电图案，用电子元件覆盖电子元件 绝缘树脂，使用第一蚀刻溶液蚀刻掉金属箔，使得保护膜不被第一蚀刻溶液溶解，或者保护膜具有比金属箔的蚀刻速度慢的蚀刻速度，并且电连接 电子元件的端子和导电图案的一部分。

公开(公告)号：US20090174045A1

公开(公告)日：2009-07-09

申请号：US11968663

申请日：2008-01-03

Applicant: Charles L. Arvin ,  Hai P. Longworth ,  David J. Russell ,  Krystyna W. Semkow

Inventor： Charles L. Arvin ,  Hai P. Longworth ,  David J. Russell ,  Krystyna W. Semkow

IPC: H01L23/495 ,  H01L21/44

CPC classification number: H01L23/49811 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/24 ,  H05K3/243 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0341 ,  H05K2201/0769 ,  H05K2201/09481 ,  H05K2201/09563 ,  H01L2924/00

Abstract: An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu portions are formed on exposed surfaces of the electroless Cu layers, followed by formation of electrolytic Ni portions and second electrolytic Cu portions. The electrolytic Ni portions provide enhanced resistance to electromigration, while the second electrolytic Cu portions provide an adhesion layer for a solder mask and serves as an oxidation protection layer. Some of the first electrolytic Cu may be masked by lithographic means to block formation of electrolytic Ni portions and second electrolytic Cu portions thereupon as needed. Optionally, the electrolytic Ni portions may be formed directly on electroless Cu layers.

Abstract translation: 在包含芯，至少一个前金属互连层和至少一个背侧金属互连层的封装基板的每一侧上形成化学镀铜层。 在两个无电镀铜层上涂布光致抗蚀剂，并用光刻图案化。 第一电解Cu部分形成在无电解Cu层的暴露表面上，随后形成电解Ni部分和第二电解Cu部分。 电解Ni部分提供增强的电迁移阻力，而第二电解Cu部分提供用于焊接掩模的粘附层并且用作氧化保护层。 一些第一电解铜可以被光刻装置掩盖，以根据需要阻挡电解Ni部分和第二电解Cu部分的形成。 任选地，电解Ni部分可以直接形成在无电镀Cu层上。

公开(公告)号：US5139923A

公开(公告)日：1992-08-18

申请号：US634966

申请日：1991-01-03

Applicant: Ritsuji Toba ,  Kanji Murakami ,  Mineo Kawamoto

Inventor： Ritsuji Toba ,  Kanji Murakami ,  Mineo Kawamoto

IPC: H05K3/10 ,  H05K3/38 ,  H05K3/42

CPC classification number: H05K3/427 ,  H05K3/108 ,  H05K3/384 ,  H05K2201/0317 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2203/0315 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/1157 ,  H05K3/385

Abstract: In conducting wiring by masking the portion other than the portion to be wired of a metallic laminate with a photoresist for plating and subjecting only the portion to be wired to pattern plating, the provision of a noble metal layer made of gold, platinum or the like, or a metallic layer made of a metal having a larger ionization tendency than that of a metal used in the pattern plating on the metallic layer constituting the undercoat of the photoresist for plating enables the peeling of the resist for plating to be prevented and excellent fine wiring to be conducted.

Abstract translation: 在通过用金属层压体的布线部分以外的部分除去用于镀覆的光致抗蚀剂并且仅使待布线部分进行图案电镀的布线中，提供由金，铂等制成的贵金属层 或者由构成电镀用光致抗蚀剂的底涂层的金属层上的图案电镀中使用的金属离子化倾向大的金属制成的金属层能够防止镀层抗蚀剂的剥离，并且具有优异的微细 接线要进行。

公开(公告)号：US11984423B2

公开(公告)日：2024-05-14

申请号：US17166917

申请日：2021-02-03

Applicant: Skyworks Solutions, Inc.

Inventor： Sandra Louise Petty-Weeks ,  Guohao Zhang ,  Hardik Bhupendra Modi

IPC: H01Q1/00 ,  H01L23/00 ,  H01L23/66 ,  H05K1/02 ,  H05K3/24

CPC classification number: H01L24/85 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48159 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48844 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/1421 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K3/244 ,  H05K2201/0341 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/48465 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/48465 ,  H01L2224/48091 ,  H01L2924/00 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2924/1305 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/00 ,  H01L2224/45139 ,  H01L2924/00 ,  H01L2224/48844 ,  H01L2924/00 ,  H01L2224/48644 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/45139 ,  H01L2924/00011

Abstract: This disclosure relates to a transmission line for high performance radio frequency (RF) applications. One such transmission line can include a bonding layer configured to receive an RF signal, a barrier layer, a diffusion barrier layer, and a conductive layer proximate to the diffusion barrier layer. The diffusion barrier layer can have a thickness that allows a received RF signal to penetrate the diffusion barrier layer to the conductive layer. In certain implementations, the diffusion barrier layer can be nickel. In some of these implementations, the transmission line can include a gold bonding layer, a palladium barrier layer, and a nickel diffusion barrier layer.

公开(公告)号：US11869834B2

公开(公告)日：2024-01-09

申请号：US17314187

申请日：2021-05-07

Applicant: TDK CORPORATION

Inventor： Takashi Daitoku ,  Susumu Taniguchi ,  Akiko Seki ,  Atsushi Sato ,  Yuhei Horikawa ,  Makoto Orikasa ,  Hisayuki Abe

IPC: H01L23/498 ,  H01L33/62 ,  H05K1/09 ,  H01L21/48 ,  H05K3/40 ,  G06F3/044

CPC classification number: H01L23/49838 ,  G06F3/044 ,  H01L21/4857 ,  H01L23/49866 ,  H01L33/62 ,  H05K1/09 ,  H05K3/4007 ,  H01L2933/0066 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2203/04

Abstract: An electroconductive substrate, including: a base material; a foundation layer disposed on the base material; a trench formation layer disposed on the foundation layer, and an electroconductive pattern layer including metal plating. A trench including a bottom surface to which the foundation layer is exposed, is formed. The trench is filled with the electroconductive pattern layer. The foundation layer includes a mixed region which is formed from a surface of the foundation layer on the electroconductive pattern layer side towards the inside thereof, and contains metal particles which contain a metal configuring the electroconductive pattern layer, and enter the foundation layer.

公开(公告)号：US20190124763A1

公开(公告)日：2019-04-25

申请号：US16229948

申请日：2018-12-21

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Shigeru MICHIWAKI

IPC: H05K1/02 ,  H05K3/14 ,  H05K3/00 ,  H05K3/42 ,  H05K1/09 ,  H05K1/03

CPC classification number: H05K1/0284 ,  H05K1/0326 ,  H05K1/09 ,  H05K3/0014 ,  H05K3/0023 ,  H05K3/14 ,  H05K3/181 ,  H05K3/389 ,  H05K3/426 ,  H05K2201/0129 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/0347 ,  H05K2201/09118 ,  H05K2203/072 ,  H05K2203/124 ,  H05K2203/1461

Abstract: A three-dimensional wiring board production method is provided that includes: a preparation step of preparing a resin film (1) having a breaking elongation of 50% or more; a first metal film formation step of forming a first metal film (3) on a surface of the resin film; a pattern formation step of performing patterning on the first metal film to form a desired pattern; a three-dimensional molding step of performing three-dimensional molding by heating and pressurizing the resin film; and a second metal film formation step of forming a second metal film (21) on the first metal film having a pattern formed thereon. In the first metal film formation step, metal is deposited in a particle state to form the first metal film in a porous state.