公开(公告)号：US20140134448A1

公开(公告)日：2014-05-15

申请号：US14130566

申请日：2012-07-11

Applicant: Yuichiro Yamauchi ,  Satoshi Hirano ,  Shinji Saito ,  Toshihiko Hanamachi

Inventor： Yuichiro Yamauchi ,  Satoshi Hirano ,  Shinji Saito ,  Toshihiko Hanamachi

IPC: B32B15/04 ,  B05D1/12 ,  C23C28/02

CPC classification number: B32B15/04 ,  B05D1/12 ,  C04B37/026 ,  C04B2237/121 ,  C04B2237/126 ,  C04B2237/128 ,  C04B2237/34 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/346 ,  C04B2237/348 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/402 ,  C04B2237/706 ,  C23C24/04 ,  C23C28/02 ,  C23C28/30 ,  H01L21/4846 ,  H01L23/3735 ,  H01L23/498 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/83447 ,  H01L2924/1305 ,  H01L2924/13055 ,  H05K1/0306 ,  H05K3/14 ,  H05K3/38 ,  H05K2201/0341 ,  H05K2201/0355 ,  H05K2203/1344 ,  Y10T428/12056 ,  H01L2924/014 ,  H01L2924/00

Abstract: The laminated body includes a ceramic base member having an insulating property, an intermediate layer including metal or alloy as a main component formed on a surface of the ceramic base member, and a metal film layer (a circuit layer and a cooling fin) formed on a surface of the intermediate layer by accelerating a powder of metal or alloy with a gas and spraying and depositing the powder on the surface of the intermediate layer as the powder is in a solid state.

Abstract translation: 层叠体包括具有绝缘性的陶瓷基材，在陶瓷基材的表面形成有作为主要成分的金属或合金的中间层和形成在陶瓷基材的表面上的金属膜层（电路层和冷却片） 通过用气体加速金属或合金粉末的中间层的表面，并且当粉末处于固体状态时将粉末喷涂并沉积在中间层的表面上。

公开(公告)号：US08722192B2

公开(公告)日：2014-05-13

申请号：US13649333

申请日：2012-10-11

Applicant: World Properties, Inc

Inventor： Sankar K. Paul

IPC: B32B27/08 ,  B32B15/08

CPC classification number: C09J107/00 ,  B32B7/12 ,  B32B15/14 ,  C08L15/00 ,  C08L19/006 ,  C08L71/12 ,  C08L71/126 ,  C08L2666/08 ,  C08L2666/14 ,  C09J171/12 ,  H05K1/0393 ,  H05K3/386 ,  H05K2201/0133 ,  H05K2201/0158 ,  H05K2201/0355 ,  Y10T428/273 ,  Y10T428/2804 ,  Y10T428/2878 ,  Y10T428/2883 ,  Y10T428/31511 ,  Y10T428/31696 ,  Y10T428/31855

Abstract: A circuit material, comprising a conductive metal layer or a dielectric circuit substrate layer and an adhesive layer disposed on the conductive metal layer or the dielectric substrate layer, wherein the adhesive comprises a poly(arylene ether) and a polybutadiene or polyisoprene polymer.

Abstract translation: 一种电路材料，包括导电金属层或介电电路衬底层和设置在导电金属层或介电衬底层上的粘合剂层，其中粘合剂包括聚（亚芳基醚）和聚丁二烯或聚异戊二烯聚合物。

公开(公告)号：US20140027164A1

公开(公告)日：2014-01-30

申请号：US13953881

申请日：2013-07-30

Applicant: Zhen Ding Technology Co., Ltd. ,  FuKui Precision Component (Shenzhen) Co., Ltd.

Inventor： RUI-WU LIU ,  MING-JAAN HO ,  XIAN-QIN HU

IPC: H05K1/09 ,  H05K3/10

CPC classification number: H05K1/09 ,  H05K1/02 ,  H05K3/00 ,  H05K3/06 ,  H05K3/067 ,  H05K3/068 ,  H05K3/10 ,  H05K3/243 ,  H05K3/244 ,  H05K3/26 ,  H05K3/282 ,  H05K3/288 ,  H05K2201/0108 ,  H05K2201/0355 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/075 ,  H05K2203/1545 ,  H05K2203/1572 ,  Y10T29/49155

Abstract: This disclosure relates to a printed circuit board comprising a light-pervious insulation layer, a patterned electrically conductive layer and a light-pervious overlay. The patterned electrically conductive layer includes a first black oxide layer, a copper layer and a second black oxide layer. The copper layer includes two opposite surfaces and a plurality of inner surfaces interconnecting the two opposite surfaces of the copper layer. The first black oxide layer is formed on one of the surfaces, and the second black oxide layer is formed on the other surface and the inner surfaces. The patterned electrically conductive layer is arranged on the light-pervious insulation layer. The light-pervious overlay is arranged on the second black oxide layer. A method for manufacturing the printed circuit board is also provided in this disclosure.

Abstract translation: 本公开涉及一种印刷电路板，其包括透光绝缘层，图案化导电层和透光覆盖层。 图案化导电层包括第一黑色氧化物层，铜层和第二黑色氧化物层。 铜层包括互连铜层的两个相对表面的两个相对表面和多个内表面。 第一黑色氧化物层形成在一个表面上，并且第二黑色氧化物层形成在另一个表面和内表面上。 图案化导电层设置在透光绝缘层上。 透光性覆盖层布置在第二黑色氧化物层上。 在本公开中还提供了制造印刷电路板的方法。

公开(公告)号：US08632874B2

公开(公告)日：2014-01-21

申请号：US12813556

申请日：2010-08-23

Applicant: Sankar Paul ,  Scott D. Kennedy ,  Dirk M. Baars

Inventor： Sankar Paul ,  Scott D. Kennedy ,  Dirk M. Baars

IPC: B32B25/02 ,  B32B25/08 ,  H01L49/00

CPC classification number: H05K3/4626 ,  B32B3/04 ,  B32B3/08 ,  B32B3/18 ,  B32B3/30 ,  B32B5/08 ,  B32B5/16 ,  B32B5/30 ,  B32B7/12 ,  B32B15/06 ,  B32B15/08 ,  B32B15/14 ,  B32B15/16 ,  B32B15/20 ,  B32B25/08 ,  B32B25/14 ,  B32B27/08 ,  B32B27/12 ,  B32B27/14 ,  B32B27/20 ,  B32B27/26 ,  B32B27/285 ,  B32B27/302 ,  B32B27/32 ,  B32B27/38 ,  B32B2255/10 ,  B32B2255/205 ,  B32B2260/025 ,  B32B2260/046 ,  B32B2262/0269 ,  B32B2262/101 ,  B32B2262/14 ,  B32B2264/10 ,  B32B2264/102 ,  B32B2264/104 ,  B32B2264/12 ,  B32B2270/00 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/30 ,  B32B2307/302 ,  B32B2307/3065 ,  B32B2307/308 ,  B32B2307/7265 ,  B32B2457/00 ,  B32B2457/08 ,  C08G65/485 ,  C08K3/013 ,  C08L9/00 ,  C08L13/00 ,  C08L15/00 ,  C08L19/006 ,  C08L51/04 ,  C08L71/12 ,  C08L71/126 ,  C08L2666/08 ,  C08L2666/14 ,  C09J107/00 ,  C09J113/00 ,  C09J171/12 ,  H05K1/0393 ,  H05K3/00 ,  H05K3/462 ,  H05K3/4641 ,  H05K3/4676 ,  H05K2201/0133 ,  H05K2201/0158 ,  H05K2201/0355 ,  H05K2201/10378 ,  Y10T156/10 ,  Y10T428/24802 ,  Y10T428/263 ,  Y10T428/31544 ,  Y10T428/31931 ,  C08L2666/04

Abstract: A circuit subassembly, comprising a dielectric layer formed from a dielectric composition comprising, based on the total volume of the composition: about 15 to about 65 volume percent of a dielectric filler; and about 35 to about 85 volume percent of a thermosetting composition comprising: a poly(arylene ether), and a carboxy-functionalized polybutadiene or polyisoprene polymer.

Abstract translation: 一种电路子组件，包括由电介质组合物形成的电介质层，所述电介质层包含基于所述组合物的总体积：约15至约65体积％的介电填料; 和约35至约85体积％的热固性组合物，其包含：聚（亚芳基醚）和羧基官能化聚丁二烯或聚异戊二烯聚合物。

公开(公告)号：US08631566B2

公开(公告)日：2014-01-21

申请号：US12546454

申请日：2009-08-24

Applicant: Petteri Palm ,  Tuomas Waris

Inventor： Petteri Palm ,  Tuomas Waris

IPC: H05K3/30 ,  H01R43/00

CPC classification number: H05K1/188 ,  H01L21/568 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/82039 ,  H01L2224/83192 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/187 ,  H05K3/205 ,  H05K3/305 ,  H05K2201/0355 ,  H05K2201/0969 ,  H05K2201/10674 ,  H05K2203/1469 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49146 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for manufacturing a circuit board structure comprising at least one electrical component. The method comprises the steps of fabricating a conductive pattern on the surface of an essentially plane-like layer on the back side of the plane-like layer, and forming an electrical contact between the at least one electrical component and the conductive pattern. The method further comprises the steps of attaching the at least one electrical component to the back side of the plane-like layer after the fabrication of the conductive pattern, molding encapsulation material on the back side of the plane-like layer so that the encapsulation material at least partly encloses the at least one electrical component attached to the back side of the plane-like layer, and forming holes through the conductive pattern at positions where terminals of the at least one electrical component is attached to the back side of the plane-like layer and become positioned when the at least one electrical component is attached to the circuit board structure.

Abstract translation: 一种用于制造包括至少一个电气部件的电路板结构的方法。 该方法包括以下步骤：在平面状层的背侧上的基本上平面状的层的表面上制造导电图案，并且在至少一个电气部件和导电图案之间形成电接触。 该方法还包括以下步骤：在制造导电图案之后将至少一个电气部件附接到平面状层的背面，在平面状层的背面上成型封装材料，使得封装材料 至少部分地包围附接到所述平面状层的背面的所述至少一个电气部件，以及在所述至少一个电气部件的端子附接到所述平面状层的背面的位置处，通过所述导电图案形成孔， 并且当至少一个电气部件附接到电路板结构时变得定位。

公开(公告)号：US08613136B2

公开(公告)日：2013-12-24

申请号：US12614576

申请日：2009-11-09

Applicant: Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

Inventor： Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

IPC: H01K3/10

CPC classification number: H05K1/185 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/188 ,  H05K3/382 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract translation: 通过提供具有第一绝缘层和导电膜的层叠体的方法制造印刷线路板。 通过去除导电膜的至少一部分，在层压体中形成对准标记。 将电子部件放置在基于对准标记确定的位置上设置在第一绝缘层上的粘合剂层上。 在将电子部件封装在第二绝缘层的开口内之后，在基于用于确定电子部件的位置的对准标记确定的位置处形成暴露电子部件的端子的通孔。 通孔导体形成在通孔中，导电层形成在导电膜上并被图案化以形成连接到通孔导体的导电电路。

公开(公告)号：US08591750B2

公开(公告)日：2013-11-26

申请号：US12659893

申请日：2010-03-24

Applicant: Hiroyuki Uematsu ,  Kenichi Kawabata ,  Kenji Nagase

Inventor： Hiroyuki Uematsu ,  Kenichi Kawabata ,  Kenji Nagase

IPC: H01B13/00 ,  H05K1/11 ,  H05K1/14

CPC classification number: H05K3/427 ,  H05K3/002 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0041 ,  H05K3/0044 ,  H05K3/061 ,  H05K3/064 ,  H05K3/382 ,  H05K3/389 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K2201/0394 ,  H05K2203/025 ,  H05K2203/0353 ,  H05K2203/054 ,  H05K2203/0585 ,  H05K2203/0733

Abstract: Provided is a method for manufacturing a multilayer wiring board, whereby even if the multilayer wiring board suffers warping or irregularities, thin-film patterns with great uniformity that are to be used as a mask for forming a wiring layer can be obtained in a simple way. A primer-coated metal foil 20 composed of a primer resin layer 21 and a metal layer 22 is placed on a surface of a double-face CCL 10, which is prepared by applying metal layers 12 and 13 onto the surfaces of a support base 11, and the primer-coated metal foil 20 and the double-face CCL 10 are bonded and the primer resin layer 21 is cured. A via Vb is thereafter formed from the metal layer 22 side, and a metal-plate layer 30 is formed on the resulting metal layer 22. After that, the etched down metal-plate layer 30 and the metal layer 22 are patterned, and using the patterned layers as a mask, the primer resin layer 21 is patterned. Using the patterned primer resin layer 21 as a mask, the metal layer 12 of the double-face CCL 10 and the metal-plate layer 30 are patterned to form a wiring pattern.

Abstract translation: 提供一种多层布线板的制造方法，即使多层布线板发生翘曲或不均匀，也可以以简单的方式获得用作形成布线层的掩模的具有均匀性的薄膜图案 。 将由底漆树脂层21和金属层22构成的底漆涂布金属箔20放置在双面CCL 10的表面上，该双面CCL 10通过将金属层12和13施加到支撑基底11的表面上而制备 并且底漆涂覆的金属箔20和双面CCL 10被粘合，底漆树脂层21固化。 之后，从金属层22侧形成通孔Vb，在所得到的金属层22上形成金属板层30.之后，对蚀刻后的金属板层30和金属层22进行图案化，使用 作为掩模的图案化层，对底漆树脂层21进行图案化。 使用图案化底漆树脂层21作为掩模，将双面CCL 10的金属层12和金属板层30图案化以形成布线图案。

公开(公告)号：US08580390B2

公开(公告)日：2013-11-12

申请号：US13141995

申请日：2009-12-22

Applicant: Keisuke Yamanishi ,  Kengo Kaminaga ,  Ryo Fukuchi

Inventor： Keisuke Yamanishi ,  Kengo Kaminaga ,  Ryo Fukuchi

IPC: H05K3/38

CPC classification number: C23C30/00 ,  B32B15/01 ,  B32B15/20 ,  B32B2307/306 ,  B32B2307/406 ,  B32B2307/50 ,  B32B2307/732 ,  B32B2457/08 ,  C22C9/00 ,  C23C22/05 ,  C23F1/02 ,  C25D1/04 ,  C25D5/022 ,  C25D5/12 ,  C25D7/0614 ,  H05K3/06 ,  H05K3/067 ,  H05K3/384 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2203/0723 ,  Y10T428/12438 ,  Y10T428/12514 ,  Y10T428/12569 ,  Y10T428/12583 ,  Y10T428/1259 ,  Y10T428/12611 ,  Y10T428/1266 ,  Y10T428/12792 ,  Y10T428/12847 ,  Y10T428/12861 ,  Y10T428/1291 ,  Y10T428/12944 ,  Y10T428/273

Abstract: Provided is a rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, wherein the copper foil comprises a heat resistance layer composed of zinc or zinc alloy or its oxide formed on an etching side of the rolled copper foil or electrolytic copper foil, and a layer of nickel or nickel alloy, which is a metal or alloy with a lower etching rate than copper, formed on the heat resistance layer. This invention aims to prevent sagging caused by the etching, to form a uniform circuit having the intended circuit width, and to shorten the time of forming a circuit by etching as much as possible, when forming a circuit by etching a copper foil of the copper-clad laminate; and also aims to make the thickness of the nickel or nickel alloy layer as thin as possible, to inhibit oxidation when exposed to heat, to prevent tarnish (discoloration) known as “YAKE”, to improve the etching properties in pattern etching, and to prevent the occurrence of short circuits and defects in the circuit width.

Abstract translation: 提供一种用于通过蚀刻形成电路的电子电路的卷绕铜箔或电解铜箔，其中铜箔包括由锌或锌合金构成的耐热层或其在轧制的蚀刻侧上形成的氧化物 铜箔或电解铜箔，和形成在耐热层上的，具有比铜蚀刻速率低的金属或合金的镍或镍合金层。 本发明旨在防止蚀刻引起的下垂，形成具有预期电路宽度的均匀电路，并且通过蚀刻形成电路时可尽可能地缩短形成电路的时间，当通过蚀刻铜箔的铜箔 单层层压板 并且还旨在使镍或镍合金层的厚度尽可能薄，以防止暴露于热时的氧化，以防止称为“YAKE”的变色（变色），以改善图案蚀刻中的蚀刻性能，并且 防止电路宽度短路和缺陷的发生。

公开(公告)号：US08568856B2

公开(公告)日：2013-10-29

申请号：US11992209

申请日：2006-08-22

Applicant: Katsuyuki Tsuchida ,  Hironori Kobayashi ,  Ryu Murakami ,  Masashi Kumagai

Inventor： Katsuyuki Tsuchida ,  Hironori Kobayashi ,  Ryu Murakami ,  Masashi Kumagai

IPC: D06N7/04

CPC classification number: H05K1/09 ,  B32B15/08 ,  B32B15/20 ,  B32B27/281 ,  B32B2307/206 ,  H05K1/0346 ,  H05K1/0393 ,  H05K3/108 ,  H05K3/28 ,  H05K3/382 ,  H05K3/388 ,  H05K2201/0355 ,  H05K2201/098 ,  H05K2203/0723 ,  Y10T428/24355

Abstract: The invention provides a two-layer flexible substrate free of surface defects and having excellent etching characteristics and adherence to a resist.The two-layer flexible substrate has a copper layer provided on one or both faces of an insulator film without using an adhesive, wherein the surface roughness (Ra) of the copper layer is 0.10 to 0.25 μm, and wherein the average crystal grain size [of copper] is no greater than 0.8 μm at 1 μm from the insulator film in the cross-section of the copper layer. Preferably, the insulator film is a polyimide film.

Abstract translation: 本发明提供一种没有表面缺陷且具有优异的蚀刻特性和对抗蚀剂的粘附性的双层柔性基材。 双层柔性基板在不使用粘合剂的情况下，在绝缘膜的一面或两面上具有铜层，其中铜层的表面粗糙度（Ra）为0.10〜0.25μm，平均结晶粒径[ 的铜]在铜层的截面中距离绝缘体膜1m时不大于0.8μm。 优选地，绝缘膜是聚酰亚胺膜。

公开(公告)号：US20130279207A1

公开(公告)日：2013-10-24

申请号：US13849636

申请日：2013-03-25

Applicant: LITE-ON ELECTRONICS(GUANGZHOU)LIMITED ,  LITE-ON TECHNOLOGY CORP.

Inventor： WEI-CHENG YU ,  CHI-CHE WU ,  LIANG-HONG WANG

IPC: H02M3/335

CPC classification number: H02M7/217 ,  H02M1/08 ,  H02M1/14 ,  H02M1/34 ,  H02M3/335 ,  H02M3/33507 ,  H02M3/33592 ,  H02M2001/0048 ,  H02M2001/348 ,  H05K1/0203 ,  H05K1/092 ,  H05K1/111 ,  H05K1/117 ,  H05K1/141 ,  H05K1/181 ,  H05K2201/0355 ,  H05K2201/10166 ,  Y02B70/1475

Abstract: A power supply device includes a main unit and a power switching module. The main unit includes a primary circuit board, a transformer including a primary and a secondary coil, a primary-side circuit and a secondary-side circuit. The power switching module includes a separate PCB formed with at least two connection pads and two conductive tracks, and at least one power switching element disposed on the PCB and having two terminals respectively connected to the two connection pads through the two conductive tracks. The power switching module is in the form of a separate PCB that is electrically connected to the primary- or secondary-side circuits through the two connection pads.

Abstract translation: 电源装置包括主单元和电源开关模块。 主单元包括主电路板，包括初级和次级线圈的变压器，初级侧电路和次级侧电路。 电源开关模块包括形成有至少两个连接焊盘和两个导电轨道的单独PCB，以及设置在PCB上的至少一个电源开关元件，并且具有通过两个导电轨道分别连接到两个连接焊盘的两个端子。 电源开关模块是单独的PCB的形式，其通过两个连接焊盘电连接到初级或次级侧电路。