公开(公告)号：US20170317438A1

公开(公告)日：2017-11-02

申请号：US15523087

申请日：2015-11-03

Applicant: ROSENBERGER HOCHFREQUENZTECHNIK GMBH & CO. KG

Inventor： Sandeep Sankararaman

IPC: H01R12/53 ,  H01R13/6471 ,  H01R12/55 ,  H05K1/02 ,  H05K1/11

CPC classification number: H01R12/53 ,  H01R12/526 ,  H01R12/55 ,  H01R13/6471 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/10378

Abstract: The invention relates to an electric interface, in particular an interposer, having a first connection plane with at least one first contact surface pair, each of which has a first and second contact surface, and a second connection plane with at least one second contact surface pair, each of which has a third and a fourth contact surface. For each of a first and second contact surface pair, a first electric connection electrically connects the first contact surface of the first connection plane to the third contact surface of the second connection plane, and a second electric connection electrically connects the second contact surface of the first connection plane to the fourth contact surface of the second connection plane. The first electric connection between the first and third contact surface has a specified first geometric length, and the second electric connection between the second and fourth contact surface has a specified second geometric length, the first and second geometric length being different.

公开(公告)号：US09799594B2

公开(公告)日：2017-10-24

申请号：US15219803

申请日：2016-07-26

Applicant: FUJIFILM Corporation

Inventor： Kosuke Yamashita

IPC: H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H05K3/40 ,  H05K3/46 ,  H05K1/02 ,  H05K1/03 ,  H05K3/36 ,  C25D3/00 ,  C23C18/00 ,  H05K1/14

CPC classification number: H01L23/49838 ,  C23C18/00 ,  C23C18/1653 ,  C23C18/54 ,  C25D3/00 ,  C25D3/38 ,  C25D5/48 ,  C25D11/045 ,  C25D11/08 ,  C25D11/12 ,  C25D11/16 ,  C25D11/20 ,  C25F3/20 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/144 ,  H05K3/368 ,  H05K3/4038 ,  H05K3/4611 ,  H05K2201/042 ,  H05K2201/10378 ,  H05K2203/0315

Abstract: The present invention is to provide a microstructure capable of improving the withstand voltage of an insulating substrate while securing fine conductive paths, a multilayer wiring board, a semiconductor package, and a microstructure manufacturing method. The microstructure of the present invention has an insulating substrate having a plurality of through holes, and conductive paths consisting of a conductive material containing metal filling the plurality of through holes, in which an average opening diameter of the plurality of through holes is 5 nm to 500 nm, an average value of the shortest distances connecting the through holes adjacent to each other is 10 nm to 300 nm, and a moisture content is 0.005% or less with respect to the total mass of the microstructure.

公开(公告)号：US20170273183A1

公开(公告)日：2017-09-21

申请号：US15610658

申请日：2017-06-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Koichiro KAWASAKI ,  Taku KIKUCHI ,  Takashi KITAHARA ,  Hiroki NOTO

IPC: H05K1/18 ,  H03H9/02 ,  H05K3/30 ,  H01L41/047 ,  H05K1/02 ,  H05K3/28

CPC classification number: H05K1/18 ,  H01L23/00 ,  H01L23/28 ,  H01L23/34 ,  H01L41/047 ,  H01L2924/0002 ,  H03H3/08 ,  H03H9/02834 ,  H03H9/0542 ,  H03H9/059 ,  H03H9/1071 ,  H04B1/38 ,  H05K1/0203 ,  H05K1/0216 ,  H05K3/284 ,  H05K3/30 ,  H05K2201/0707 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10378 ,  H05K2201/10734 ,  H01L2924/00

Abstract: An electronic component includes an electronic component element including first and second main surfaces, a heat-dissipation accelerating member on the first main surface, a sealing resin layer sealing the electronic component element, and a shielding member provided on the sealing resin layer and electrically connected to the heat-dissipation accelerating member. The heat-dissipation accelerating member includes fourth and fifth main surfaces. The electronic component includes a connecting member disposed on the fifth main surface of the heat-dissipation accelerating member and electrically connecting at least one portion of the heat-dissipation accelerating member and the shielding member. The connecting member has a higher thermal conductivity than the sealing resin layer. The contact area between the heat-dissipation accelerating member and the connecting member is smaller than the area of the fifth main surface.

公开(公告)号：US09768536B2

公开(公告)日：2017-09-19

申请号：US15053412

申请日：2016-02-25

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Kevin Leigh ,  George Megason

IPC: H01R12/00 ,  H01R12/70 ,  H05K7/10 ,  H05K3/32 ,  H01R12/71

CPC classification number: H01R12/7076 ,  H01R12/712 ,  H01R12/714 ,  H05K3/325 ,  H05K7/1092 ,  H05K2201/0311 ,  H05K2201/10325 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: A socket (130) employs a substrate (310) including a conductive network. An array of first contacts (136) is on a top surface of the substrate (310) and arranged to engage an integrated circuit (110). An array of second contacts (138) is on a bottom surface of the substrate (310) and arranged to engage a circuit board (120). The conductive network electrically connects the first contacts (136) respectively to the second contacts (138), and the first contacts (136) include a routed first contact (136′) that the conductive network routes horizontally in or on the substrate (310).

公开(公告)号：US09756724B2

公开(公告)日：2017-09-05

申请号：US13252256

申请日：2011-10-04

Applicant: Rabindra N. Das ,  Kostas I. Papathomas ,  Voya R. Markovich

Inventor： Rabindra N. Das ,  Kostas I. Papathomas ,  Voya R. Markovich

IPC: H05K3/40 ,  H05K1/03 ,  H05K3/46 ,  B23K26/382 ,  B23K26/40 ,  H01B1/22 ,  H05K1/09 ,  B23K103/00 ,  B23K101/40 ,  B23K103/16

CPC classification number: H05K1/0313 ,  B23K26/382 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/16 ,  B23K2103/172 ,  B23K2103/52 ,  H01B1/22 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01322 ,  H01L2924/15311 ,  H05K1/097 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0257 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10378 ,  H05K2203/0425 ,  H05K2203/1152 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a metallic component including nano-particles and may include additional elements such as solder or other metal micro-particles, as well as a conducting polymer and organic. The particles of the paste composition sinter and, depending on what additional elements are added, melt as a result of lamination to thereby form effective contiguous circuit paths through the paste. A method of making such a substrate is also provided, as is an electrical assembly utilizing the substrate and including an electronic component such as a semiconductor chip coupled thereto.

公开(公告)号：US09735085B2

公开(公告)日：2017-08-15

申请号：US15119547

申请日：2015-01-30

Applicant: MITSUBISHI MATERIALS CORPORATION

Inventor： Nobuyuki Terasaki ,  Yoshiyuki Nagatomo

IPC: H05K7/00 ,  H01L23/373 ,  H01L25/07 ,  H01L25/18 ,  C04B37/02 ,  H01L23/15 ,  B23K1/00 ,  B23K35/30 ,  H05K1/18

CPC classification number: H01L23/3735 ,  B23K1/0016 ,  B23K35/302 ,  C04B37/026 ,  C04B2235/656 ,  C04B2235/6567 ,  C04B2237/121 ,  C04B2237/122 ,  C04B2237/124 ,  C04B2237/126 ,  C04B2237/127 ,  C04B2237/128 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/402 ,  C04B2237/407 ,  C04B2237/60 ,  C04B2237/708 ,  C04B2237/72 ,  H01L23/15 ,  H01L25/07 ,  H01L25/18 ,  H01L2224/32225 ,  H01L2224/83101 ,  H05K1/181 ,  H05K2201/10378

Abstract: There is provided a bonded body of the invention in which a ceramic member formed of a ceramic containing Al and a Cu member formed of Cu or a Cu alloy are bonded to each other, in which a bonding portion is formed between the ceramic member and the Cu member, an active metal compound region formed of a compound containing active metal is formed on the bonded portion on the ceramic member side, and an Al concentration of the bonding portion having a thickness range of 0.5 μm to 3 μm from one surface of the active metal compound region on the Cu member side towards the Cu member side is in a range of 0.5 at % to 15 at %.

公开(公告)号：US20170142824A1

公开(公告)日：2017-05-18

申请号：US14944733

申请日：2015-11-18

Applicant: Raytheon Company

Inventor： Angelo M. Puzella ,  John B. Francis ,  Dennis W. Mercier ,  John Sangiolo ,  Mark Ackerman ,  Ethan S. Heinrich

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/11

CPC classification number: H05K1/0237 ,  H01R12/523 ,  H01R12/714 ,  H01R24/50 ,  H01R24/54 ,  H05K1/0216 ,  H05K1/0222 ,  H05K1/09 ,  H05K1/115 ,  H05K1/144 ,  H05K1/18 ,  H05K1/183 ,  H05K2201/10378

Abstract: An radio-frequency (RF) interposer enables low-cost, high-performance RF interconnection of two or more large-area printed wiring boards (PWBs). The RF interposer may be provided as a multi-port coaxial structure embedded in a metal (or metalized) carrier. The RF interposer may include one or more conductive shims having spring fingers to provide contact across air-gaps between a PWB RF ground plane and a ground plane of the RF interposer. Retractable pins may be used as the coaxial transmission line center conductors. The RF interposer may be provided as an N×M grid of unit cells each having one or more RF ports and a cavities to provide clearance for a PWB component.

公开(公告)号：US20170141016A1

公开(公告)日：2017-05-18

申请号：US15420182

申请日：2017-01-31

Applicant: Ubotic Company Limited

Inventor： Chun Ho FAN

IPC: H01L23/495 ,  H05K1/02 ,  H01L21/56 ,  H01L23/057 ,  H01L21/48

CPC classification number: H01L23/49506 ,  H01L21/4839 ,  H01L21/50 ,  H01L21/56 ,  H01L23/057 ,  H01L23/495 ,  H01L23/49517 ,  H01L23/49551 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K2201/068 ,  H05K2201/10378 ,  H01L2924/00

Abstract: A cavity package is provided. The package can include a metal leadframe and a substrate attached to an interposer formed as part of the leadframe. The substrate typically has a coefficient of thermal expansion matched to the coefficient of thermal expansion of a semiconductor device to be affixed to the substrate. The semiconductor device is typically attached to an exposed top surface of the substrate. The cavity package also includes a plastic portion molded to the leadframe forming a substrate cavity. The substrate cavity allows access to the exposed top surface of the substrate for affixing the semiconductor device. The cavity package also include a connective element for grounding a lid through an electrical path from the lid to the interposer.

公开(公告)号：US09648729B1

公开(公告)日：2017-05-09

申请号：US14947574

申请日：2015-11-20

Applicant: Raytheon Company

Inventor： Tse E. Wong ,  Shea Chen ,  Hoyoung C. Choe

IPC: H01L23/52 ,  H05K1/02 ,  H01L23/492 ,  H01L23/498 ,  H01L25/065 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H01L23/4924 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L25/065 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/0305 ,  H05K2201/049 ,  H05K2201/068 ,  H05K2201/09036 ,  H05K2201/094 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/047 ,  Y02P70/613

Abstract: A stress reduction interposer is provided for disposition between first and second solder materials of first and second electronic devices, respectively. The stress reduction interposer includes a plate element having a central portion and a periphery surrounding the central portion and being formed to define first cavities having an upper area limit at the periphery and a second cavity having a lower area limit, which is higher than the upper area limit, at the central portion and third and fourth solder materials being disposable in the second cavity and in the first cavities, respectively, to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second and fourth solder materials.

公开(公告)号：US09622350B2

公开(公告)日：2017-04-11

申请号：US14040637

申请日：2013-09-28

Applicant: Mihir K. Roy ,  Mathew J. Manusharow

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H05K1/14 ,  H05K3/20 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18

CPC classification number: H05K1/116 ,  H05K1/141 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/107 ,  H05K3/182 ,  H05K3/207 ,  H05K3/422 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49128

Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.