公开(公告)号：US10114941B2

公开(公告)日：2018-10-30

申请号：US15246405

申请日：2016-08-24

Applicant: Altera Corporation

Inventor： Bruce B. Pedersen

IPC: H04L9/32 ,  G06F21/44 ,  G06F21/56 ,  G06F21/57 ,  G06F21/72 ,  G06F21/76

Abstract: The invention discloses a method of authenticating data stored in an integrated circuit. The method includes storing randomized data in the integrated circuit such that the randomized data occupies each address space of the memory circuit that is not occupied by the stored data. The method also includes generating a first digital signature using the integrated circuit in response to authenticating a concatenation of the stored data and the first copy of randomized data. The method further includes generating a second digital signature in response to authenticating concatenation of a manufacturer-provided copy of the stored data and the second copy of randomized data using a computer-implemented authentication application and authenticating the data stored in the integrated circuit according to whether the first signature matches the second signature.

公开(公告)号：US10110233B2

公开(公告)日：2018-10-23

申请号：US15190716

申请日：2016-06-23

Applicant: Altera Corporation

Inventor： Martin Langhammer

IPC: G06F17/50 ,  H03K19/177 ,  G06F15/82

Abstract: A programmable integrated circuit may include soft and hard logic for implementing a reduced instruction set computing (RISC) processor. Processor generator tools implemented on specialized computing equipment may be used to specify desired parameters for the processor architecture, including the data word size of one or more data paths, the instruction word size, and a set of instruction formats. The processor generator tools may also be used to determine the appropriate amount of pipelining that is required for each data path to satisfy performance criteria. The processor generator tools can also be used to analyze the processor architecture and to provide options for mitigating potential structural and data hazards.

公开(公告)号：US20180293343A1

公开(公告)日：2018-10-11

申请号：US16002988

申请日：2018-06-07

Applicant: Altera Corporation

Inventor： Nishanth Sinnadurai ,  Gordon Raymond Chiu

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2217/84

Abstract: A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design. For example, the circuit design computing equipment may preserve the register retiming solution from the first circuit design implementation for portions of the second circuit design that are outside the region-of-change and incrementally create graphs that allow to incrementally solve the register retiming problem during the second circuit design implementation.

公开(公告)号：US10073989B2

公开(公告)日：2018-09-11

申请号：US15589671

申请日：2017-05-08

Applicant: Altera Corporation

Inventor： Bruce B. Pedersen ,  Dirk A. Reese

IPC: G06F7/38 ,  G06F21/79 ,  G11C11/419 ,  G11C7/20 ,  G06F21/76

CPC classification number: G06F21/79 ,  G06F21/76 ,  G11C7/20 ,  G11C11/419

Abstract: Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory.

公开(公告)号：US20180239738A1

公开(公告)日：2018-08-23

申请号：US15954078

申请日：2018-04-16

Applicant: Altera Corporation

Inventor： Chee Hak Teh ,  Arifur Rahman

IPC: G06F15/78 ,  G06F1/08 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F15/7803 ,  G06F1/06 ,  G06F1/10 ,  G06F13/4022 ,  G06F13/4234 ,  G06F13/4291 ,  G06F15/7864 ,  Y02D10/14 ,  Y02D10/151

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US10043716B2

公开(公告)日：2018-08-07

申请号：US15243732

申请日：2016-08-22

Applicant: Altera Corporation

Inventor： Dustin Do ,  Andy L. Lee ,  Giles V. Powell ,  Bradley Jensen ,  Swee Aun Lau ,  Wuu-Cherng Lin ,  Thomas H. White

IPC: H01L21/8234 ,  H01L21/3205 ,  H01L21/762 ,  H01L27/02 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L21/823493 ,  H01L21/32055 ,  H01L21/76224 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823871 ,  H01L21/823892 ,  H01L27/0207 ,  H01L29/7833

Abstract: Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

公开(公告)号：US20180218094A1

公开(公告)日：2018-08-02

申请号：US15940881

申请日：2018-03-29

Applicant: ALTERA CORPORATION

Inventor： Adam Titley

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5045 ,  G06F17/5054

Abstract: Aspects of this disclosure relate generally to electronic design automation, and more specifically, to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. Some innovative aspects can be implemented in computer-readable media, systems and methods capable of accessing an algorithmic description representation of a circuit design. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. The media, systems and methods also are capable of compiling the algorithmic description representation of the circuit design. In some implementations, the compiling includes identifying the at least one construct, accessing a first safety data type definition associated with the first safety data type, and generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition. The second representation can be provided in a second language and include at least one safety feature for a portion of the circuit design associated with the at least one construct.

公开(公告)号：US20180217657A1

公开(公告)日：2018-08-02

申请号：US15940825

申请日：2018-03-29

Applicant: Altera Corporation

Inventor： Ting Lok Song

IPC: G06F1/32 ,  H04L7/033 ,  H03L7/08 ,  H03K3/012

CPC classification number: G06F1/3237 ,  G06F1/3253 ,  H03K3/012 ,  H03K19/0016 ,  H03L7/0807 ,  H04L7/0331 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

Abstract: Systems and methods are provided for managing power of a device coupled with a transceiver module, in communication with a high-speed interface. In one aspect, a dynamic clock trunk tree associated with the transceiver module is controlled by a trunk driver having a first clock tree gate. A dynamic clock leaf tree associated with the device is controlled by a leaf driver having a second clock tree gate. Significant power savings may be achieved, for example, by triggering activation of clock gating mechanisms.

公开(公告)号：US20180211697A1

公开(公告)日：2018-07-26

申请号：US15878182

申请日：2018-01-23

Applicant: Altera Corporation

Inventor： Chee Hak Teh

IPC: G11C7/22 ,  G06F13/16

CPC classification number: G11C7/22 ,  G06F13/1631 ,  G06F13/1642 ,  H03K19/17744 ,  H03K19/1776

Abstract: Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in third clock domain that is an integer multiple of the second clock domain. The user logic interface may include only user-dependent blocks. The physical layer interface may include memory protocol agnostic blocks and/or memory protocol specific blocks. The memory controller may include both memory protocol agnostic blocks and memory protocol dependent blocks. The memory controller may include one or more color pipelines for scheduling memory requests in a parallel arbitration scheme.

公开(公告)号：US10027327B2

公开(公告)日：2018-07-17

申请号：US15227718

申请日：2016-08-03

Applicant: Altera Corporation

Inventor： David Lewis

IPC: H03K19/173 ,  G11C13/00 ,  H03K19/177 ,  G01R21/133

Abstract: Various structures and methods are disclosed related to routing and programming circuitry on integrated circuits (“IC”) that have arrays of programmable resistive switches. In some embodiments, routing structures utilize densely populated resistive switch arrays to provide for efficient selection circuits that route into and out of logic regions. In other embodiments, programming circuitry is provided to help maintain relatively consistent programming current throughout an array of resistive switches to be programmed. In other embodiments, methods are provided for programming resistive switches without violating given power constraints. These and other embodiments are described further herein.