公开(公告)号：US11658026B2

公开(公告)日：2023-05-23

申请号：US17078985

申请日：2020-10-23

Applicant: Applied Materials, Inc.

Inventor： Zeqing Shen ,  Bo Qi ,  Abhijit Basu Mallick

IPC: H01L21/02 ,  C23C16/40

CPC classification number: H01L21/0228 ,  C23C16/401 ,  H01L21/02164 ,  H01L21/02211

Abstract: Methods for depositing a silicon-containing film on a substrate are described. The method comprises heating a processing chamber to a temperature greater than or equal to 200° C.; maintaining the processing chamber at a pressure of less than or equal to 300 Torr; coflowing a silicon precursor and nitrous oxide (N2O) into the processing chamber, and depositing a conformal silicon-containing film on the substrate. The silicon-containing film has dielectric constant (k-value) in a range of from about 3.8 to about 4.0, has a breakdown voltage of greater than 8 MV/cm at a leakage current of 1 mA/cm2 and has a leakage current of less than 1 nA/cm2 at 2 MV/cm.

公开(公告)号：US20230059788A1

公开(公告)日：2023-02-23

申请号：US17407553

申请日：2021-08-20

Applicant: Applied Materials, Inc.

Inventor： Bhaskar Jyoti Bhuyan ,  Zeqing Shen ,  Susmit Singha Roy ,  Abhijit Basu Mallick

IPC: H01L21/02 ,  H01L21/311

Abstract: Exemplary methods of semiconductor processing may include etching one or more features partially through a dielectric material to expose material from one or more layer pairs formed on a substrate. The methods may include halting the etching prior to penetrating fully through the dielectric material, and prior to exposing material from all layer pairs formed on the substrate. The methods may include forming a layer of carbon-containing material on the exposed material from each of the one or more layer pairs having exposed material. The methods may include etching the one or more features fully through the dielectric material to expose material for each remaining layer pair formed on the substrate.

公开(公告)号：US11495454B2

公开(公告)日：2022-11-08

申请号：US16987704

申请日：2020-08-07

Applicant: Applied Materials, Inc.

Inventor： Huiyuan Wang ,  Rick Kustra ,  Bo Qi ,  Abhijit Basu Mallick ,  Kaushik Alayavalli ,  Jay D. Pinson

IPC: H01L21/02 ,  C23C16/32 ,  C23C16/50 ,  C23C16/34 ,  C23C16/36 ,  C23C16/40

Abstract: Examples of the present technology include semiconductor processing methods to form boron-containing materials on substrates. Exemplary processing methods may include delivering a deposition precursor that includes a boron-containing precursor to a processing region of a semiconductor processing chamber. A plasma may be formed from the deposition precursor within the processing region of the semiconductor processing chamber. The methods may further include depositing a boron-containing material on a substrate disposed within the processing region of the semiconductor processing chamber, where the substrate is characterized by a temperature of less than or about 50° C. The as-deposited boron-containing material may be characterized by a surface roughness of less than or about 2 nm, and a stress level of less-than or about −500 MPa. In some embodiments, a layer of the boron-containing material may function as a hardmask.

公开(公告)号：US11462438B2

公开(公告)日：2022-10-04

申请号：US16647310

申请日：2018-09-14

Applicant: Applied Materials, Inc.

Inventor： Susmit Singha Roy ,  Srinivas Gandikota ,  Abhijit Basu Mallick ,  Amrita B. Mullick

IPC: H01L21/768 ,  C23C16/04 ,  C23C16/42 ,  C23C16/44 ,  C23C16/56

Abstract: Methods of producing a self-aligned structure are described. The methods comprise forming a metal-containing film in a substrate feature and silicidizing the metal-containing film to form a self-aligned structure comprising metal silicide. In some embodiments, the rate of formation of the self-aligned structure is controlled. In some embodiments, the amount of volumetric expansion of the metal-containing film to form the self-aligned structure is controlled. Methods of forming self-aligned vias are also described.

公开(公告)号：US20220246432A1

公开(公告)日：2022-08-04

申请号：US17724994

申请日：2022-04-20

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Abhijit Basu Mallick ,  Swaminathan Srinivasan ,  Rui Cheng ,  Susmit Singha Roy ,  Gaurav Thareja ,  Mukund Srinivasan ,  Sanjay Natarajan

IPC: H01L21/225 ,  H01L21/30 ,  H01L21/67 ,  H01L21/02

Abstract: Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.

公开(公告)号：US20220108888A1

公开(公告)日：2022-04-07

申请号：US17062630

申请日：2020-10-04

Applicant: Applied Materials, Inc.

Inventor： Huiyuan Wang ,  Susmit Singha Roy ,  Abhijit Basu Mallick

IPC: H01L21/02 ,  C23C16/06 ,  C23C16/24 ,  C23C16/30 ,  C23C16/32 ,  C23C16/40 ,  C23C16/02

Abstract: Methods for selectively depositing germanium containing films are disclosed. Some embodiments of the disclosure provide deposition on a bare silicon with little to no deposition on a silicon oxide surface. Some embodiments of the disclosure provide conformal films on trench sidewalls. Some embodiments of the disclosure provide superior gap fill without seams or voids.

公开(公告)号：US20220028686A1

公开(公告)日：2022-01-27

申请号：US16935385

申请日：2020-07-22

Applicant: Applied Materials, Inc. ,  National University of Singapore

Inventor： Bhaskar Bhuyan ,  Zeqing Shen ,  Bo Qi ,  Abhijit Basu Mallick ,  Xinke Wang ,  Mark Saly

IPC: H01L21/02 ,  B05D1/00

Abstract: Exemplary processing methods may include flowing a first deposition precursor into a substrate processing region to form a first portion of an initial compound layer. The first deposition precursor may include an aldehyde reactive group. The methods may include removing a first deposition effluent including the first deposition precursor from the substrate processing region. The methods may include flowing a second deposition precursor into the substrate processing region. The second deposition precursor may include an amine reactive group, and the amine reactive group may react with the aldehyde reactive group to form a second portion of the initial compound layer. The methods may include removing a second deposition effluent including the second deposition precursor from the substrate processing region. The methods may include annealing the initial compound layer to form an annealed carbon-containing material on the surface of the substrate.

公开(公告)号：US20210358744A1

公开(公告)日：2021-11-18

申请号：US17391412

申请日：2021-08-02

Applicant: Applied Materials, Inc.

Inventor： Eswaranand Venkatasubramanian ,  Srinivas Gandikota ,  Kelvin Chan ,  Atashi Basu ,  Abhijit Basu Mallick

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/455 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: A microelectronic device on a semiconductor substrate comprises: a gate electrode; and a spacer adjacent to the gate electrode, the spacer comprising: a the low-k dielectric film comprising one or more species of vanadium oxide, which is optionally doped, and an optional silicon nitride or oxide film. Methods comprise depositing a low-k dielectric film optionally sandwiched by a silicon nitride or oxide film to form a spacer adjacent to a gate electrode of a microelectronic device on a semiconductor substrate, wherein the low-k dielectric film comprises a vanadium-containing film.

公开(公告)号：US20210254210A1

公开(公告)日：2021-08-19

申请号：US17173871

申请日：2021-02-11

Applicant: Applied Materials, Inc.

Inventor： Zeqing Shen ,  Bo Qi ,  Abhijit Basu Mallick ,  Nitin K. Ingle

IPC: C23C16/40 ,  C23C16/52

Abstract: Hydrogen free (low-H) silicon dioxide layers are disclosed. Some embodiments provide methods for forming low-H layers using hydrogen-free silicon precursors and hydrogen-free oxygen sources. Some embodiments provide methods for tuning the stress profile of low-H silicon dioxide films. Further, some embodiments of the disclosure provide oxide-nitride stacks which exhibit reduced stack bow after anneal.

公开(公告)号：US20210167021A1

公开(公告)日：2021-06-03

申请号：US17171432

申请日：2021-02-09

Applicant: Applied Materials, Inc.

Inventor： Yong Wu ,  Srinivas Gandikota ,  Abhijit Basu Mallick ,  Srinivas D. Nemani

IPC: H01L23/532 ,  H01L21/768 ,  C23C16/455 ,  C23C16/26 ,  H01L21/285 ,  H01L21/3205 ,  H01L27/115

Abstract: A graphene barrier layer is disclosed. Some embodiments relate to a graphene barrier layer capable of preventing diffusion from a fill layer into a substrate surface and/or vice versa. Some embodiments relate to a graphene barrier layer that prevents diffusion of fluorine from a tungsten layer into the underlying substrate. Additional embodiments relate to electronic devices which contain a graphene barrier layer.