公开(公告)号：US09268393B2

公开(公告)日：2016-02-23

申请号：US13997295

申请日：2012-11-30

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth Sistla ,  Martin T. Rowland ,  Brian J. Griffith ,  Viktor D. Vogman ,  Joseph R. Doucette ,  Eric J. Dehaemer ,  Vivek Garg ,  Chris Poirier ,  Jeremy J. Shrall ,  Avinash N. Ananthakrishnan ,  Stephen H. Gunther

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/06 ,  G06F9/45

CPC classification number: G06F1/3234 ,  G06F1/06 ,  G06F1/324 ,  G06F8/4432 ,  Y02D10/126

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，多个图形引擎各自独立地执行图形操作; 以及功率控制单元，其耦合到所述多个核以控制所述处理器的功率消耗，其中所述功率控制单元包括功率偏移控制逻辑，以将所述处理器的功率消耗水平限制在高于限定功率极限以上 工作周期的占空比部分。 描述和要求保护其他实施例。

公开(公告)号：US09170624B2

公开(公告)日：2015-10-27

申请号：US13782473

申请日：2013-03-01

Applicant: Intel Corporation

Inventor： Krishnakanth V. Sistla ,  Jeremy Shrall ,  Stephen H. Gunther ,  Efraim Rotem ,  Alon Naveh ,  Eliezer Weissmann ,  Anil Aggarwal ,  Martin T. Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Avinash N. Ananthakrishnan ,  Jason Brandt

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

公开(公告)号：US20150269105A1

公开(公告)日：2015-09-24

申请号：US14732693

申请日：2015-06-06

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Buck W. Gremel ,  Robert G. Blankenship ,  Krishnakanth V. Sistla ,  Michael F. Cole

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F1/3203 ,  G06F1/3253 ,  G06F13/4018 ,  G06F13/4221 ,  G06F15/16 ,  Y02D10/151

Abstract: Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, link width modulation logic adjusts the width of an interconnect link. More particularly, the link width modulation logic causes the interconnect link to transition from a first width to a second width based on comparison of a utilization value associated with the interconnect link against at least one of a plurality of utilization threshold values. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与低开销利用感知链路宽度调制相关的方法和装置，以减少互连中的功耗。 在一个实施例中，链路宽度调制逻辑调整互连链路的宽度。 更具体地，链路宽度调制逻辑使得互连链路基于与互连链路相关联的利用值与多个利用阈值中的至少一个的比较从第一宽度转换到第二宽度。 还公开并要求保护其他实施例。

公开(公告)号：US12066853B2

公开(公告)日：2024-08-20

申请号：US18329492

申请日：2023-06-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/30 ,  G06F9/455

CPC classification number: G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/30101 ,  G06F9/45558 ,  G06F2009/45591 ,  Y02D10/00

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20230315143A1

公开(公告)日：2023-10-05

申请号：US18329492

申请日：2023-06-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

CPC classification number: G06F1/08 ,  G06F1/3203 ,  G06F9/30101 ,  G06F9/45558 ,  G06F1/324 ,  G06F2009/45591

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20230148150A1

公开(公告)日：2023-05-11

申请号：US17664083

申请日：2022-05-19

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/3234

CPC classification number: G06F1/3234

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

公开(公告)号：US20230131521A1

公开(公告)日：2023-04-27

申请号：US18086799

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Daniel J. Ragland ,  Guy M. Therien ,  Ankush Varma ,  Eric J. DeHaemer ,  David T. Mayo ,  Ariel Gur ,  Yoav Ben-Raphael ,  Mark P. Seconi

IPC: G06F1/3203 ,  G06F9/50 ,  G06F1/324

Abstract: In one embodiment, a processor includes: a plurality of cores each comprising a multi-threaded core to concurrently execute a plurality of threads; and a control circuit to concurrently enable at least one of the plurality of cores to operate in a single-threaded mode and at least one other of the plurality of cores to operate in a multi-threaded mode. Other embodiments are described and claimed.

公开(公告)号：US11567896B2

公开(公告)日：2023-01-31

申请号：US16916197

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Guy G. Sotomayor ,  Andrew D. Henroid ,  Robert E. Gough ,  Tod F. Schiff

IPC: G06F1/20 ,  G06F15/00 ,  G06F1/3234 ,  G06F9/455 ,  G06F9/50 ,  G06F1/26

Abstract: In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

公开(公告)号：US11442529B2

公开(公告)日：2022-09-13

申请号：US16412606

申请日：2019-05-15

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Ameya Ambardekar ,  Ankush Varma ,  Nimrod Angel ,  Nir Rosenzweig ,  Arik Gihon ,  Alexander Gendler ,  Rachid E. Rayess ,  Tamir Salus

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/3296 ,  G06F9/38 ,  G06F11/34

Abstract: In one embodiment, an apparatus comprises: a plurality of intellectual property (IP) circuits, each of the plurality of IP circuits including a configuration register to store a dynamic current budget; and a power controller coupled to the plurality of IP circuits, the power controller including a dynamic current sharing control circuit to receive current throttling hint information regarding a workload to be executed on at least some of the plurality of IP circuits and generate the dynamic current budget for each of the plurality of IP circuits based at least in part thereon. Other embodiments are described and claimed.

公开(公告)号：US11237615B2

公开(公告)日：2022-02-01

申请号：US16836686

申请日：2020-03-31

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Nir Rosenzweig ,  Krishnakanth V. Sistla ,  Ashish V. Choubal ,  Ankush Varma

IPC: G06F1/00 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3237

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.