公开(公告)号：US11515248B2

公开(公告)日：2022-11-29

申请号：US17009308

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

IPC: H01L25/18 ,  H01L23/522 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L21/56

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US10957656B2

公开(公告)日：2021-03-23

申请号：US16641601

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Kyle Yazzie ,  Naga Sivakumar Yagnamurthy ,  Pramod Malatkar ,  Chia-Pin Chiu ,  Mohit Mamodia ,  Mark J. Gallina ,  Rajesh Kumar Neerukatti ,  Joseph Bautista ,  Michael Gregory Drake

IPC: H01L23/40 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498

Abstract: Disclosed herein are integrated circuit (IC) packages with an electronic component having a patterned protective material on a face, as well as related devices and methods. In some embodiments, a computing device may include: an integrated circuit (IC) package with an electronic component having a protective material on the back face of the electronic component, where the protective material is patterned to include an area on the back face of the electronic component that is not covered by the protective material; a circuit board, where the IC package is electrically coupled to the circuit board; and a heat spreader, where the heat spreader is secured to the circuit board and in thermal contact with the area on the back face of the electronic component that is not covered by the protective material.

公开(公告)号：US10861815B2

公开(公告)日：2020-12-08

申请号：US16561965

申请日：2019-09-05

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L21/56

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BRIM substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US20200381330A1

公开(公告)日：2020-12-03

申请号：US16425264

申请日：2019-05-29

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Robert Sankman

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/42 ,  H01L25/10 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H05K1/18 ,  H05K1/14

Abstract: An integrated circuit assembly may be formed comprising at least two integrated circuit packages, wherein the at least two integrated circuit packages share a heat dissipation device. In one embodiment, the at least two integrated circuit packages may be electrically attached to an electronic card to form an intermediate integrated circuit assembly. In a further embodiment, the integrated circuit assembly may comprise at least one intermediate integrated circuit assembly electrically attached to an electronic board.

公开(公告)号：US20190297724A1

公开(公告)日：2019-09-26

申请号：US15927020

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu

IPC: H05K1/02 ,  H05K1/18 ,  H05K5/00 ,  H01G4/12 ,  H05K1/11

Abstract: Printed circuit board assembly (PCBA) technology is disclosed. A PCBA can include a printed circuit board (PCB). The PCBA can also include a capacitor operably mounted on a side of the PCB. In addition, the PCBA can include a damper material coupled to the PCB and operable to dissipate kinetic energy generated by the capacitor during operation. An electronic system including a capacitor and damping material, and a method for minimizing acoustic vibration in an electronic system are also disclosed.

公开(公告)号：US10199346B2

公开(公告)日：2019-02-05

申请号：US15873567

申请日：2018-01-17

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  Chia-Pin Chiu

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/538 ,  H01L25/16 ,  H01L23/50 ,  H01L25/18 ,  H01L23/31 ,  H01L21/56

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

公开(公告)号：US20180366444A1

公开(公告)日：2018-12-20

申请号：US15977355

申请日：2018-05-11

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu

IPC: H01L25/065 ,  H01L23/36

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include a substrate, a first die, and a second die coupled to the first die and the substrate. The substrate may include an opening. At least a portion of the die may occupy at least a portion of the opening in the substrate. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US10049987B2

公开(公告)日：2018-08-14

申请号：US15390809

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kyle Yazzie

IPC: B32B3/00 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/544 ,  H01L24/83 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/83122 ,  H01L2224/83132

Abstract: Particular embodiments described herein provide for a base, a plurality of fiducials on the base, and a fluid in one or more of each of the plurality of fiducials to increase recognition of each of the one or more fiducials that includes the fluid by one or more pattern recognition devices. In an example, the fluid is an epoxy and the fiducials are used to determine a placement of components in a component space.

公开(公告)号：US09741664B2

公开(公告)日：2017-08-22

申请号：US15147411

申请日：2016-05-05

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kinya Ichikawa ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065 ,  H01L23/31 ,  H01L25/18 ,  H01L23/498 ,  H05K1/11 ,  H05K3/34 ,  H05K3/46

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/23 ,  H01L24/24 ,  H01L24/25 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/215 ,  H01L2224/24225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15747 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/4664 ,  H05K3/4694 ,  H05K2203/013 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a technique can include creating a multidie substrate, printing an interconnect bridge on the multidie substrate, electrically coupling a first die to a second die by coupling the first and second dies through the interconnect bridge.

公开(公告)号：US09679843B2

公开(公告)日：2017-06-13

申请号：US15049500

申请日：2016-02-22

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L23/48 ,  H01L23/522 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.