公开(公告)号：US20210074704A1

公开(公告)日：2021-03-11

申请号：US16650155

申请日：2018-01-10

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Gilbert Dewey ,  Willy Rachmady ,  Patrick Morrow ,  Rishabh Mehandru

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417

Abstract: An integrated circuit structure includes a first portion of a bottom semiconductor fin extending horizontally in a length direction and vertically in a height direction, a second portion of the bottom semiconductor fin extending horizontally in the length direction and vertically in the height direction, a top semiconductor fin extending horizontally in the length direction and vertically in the height direction, and an insulator region extending horizontally in the length direction to electrically insulate the first portion of the bottom semiconductor fin from the second portion of the bottom semiconductor fin. The insulator region further extends vertically in the height direction in vertical alignment with the top semiconductor fin. The insulator region includes at least one of an insulator material and an airgap. In an embodiment, the top semiconductor fin is associated with a transistor, and the insulator region is in vertical alignment with a gate electrode of the transistor.

公开(公告)号：US10937665B2

公开(公告)日：2021-03-02

申请号：US16327713

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Harold W. Kennel ,  Patrick Morrow ,  Rishabh Mehandru ,  Stephen M. Cea

IPC: H01L21/322 ,  H01L21/265 ,  H01L21/768 ,  H01L21/38 ,  H01L21/70 ,  H01L23/26

Abstract: Methods and apparatus for gettering impurities in semiconductors are disclosed. A disclosed example multilayered die includes a substrate material, a component layer below the substrate material, and an impurity attractant region disposed in the substrate material.

公开(公告)号：US10896847B2

公开(公告)日：2021-01-19

申请号：US16539957

申请日：2019-08-13

Applicant: Intel Corporation

Inventor： Il-Seok Son ,  Colin T. Carver ,  Paul B. Fischer ,  Patrick Morrow ,  Kimin Jun

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/84 ,  H01L21/306 ,  H01L25/065 ,  H01L27/088 ,  H01L29/06

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

公开(公告)号：US20200335501A1

公开(公告)日：2020-10-22

申请号：US16957664

申请日：2018-03-02

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Patrick Morrow ,  Ravi Pillarisetty ,  Rishabh Mehandru ,  Cheng-ying Huang ,  Willy Rachmady ,  Aaron Lilak

IPC: H01L27/092 ,  H01L25/07 ,  H01L27/06 ,  H01L21/8238 ,  H01L29/778 ,  H01L29/06 ,  H01L29/78

Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.

公开(公告)号：US10763248B2

公开(公告)日：2020-09-01

申请号：US15754822

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Sansaptak W. Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Ravi Pillarisetty ,  Kimin Jun ,  Patrick Morrow ,  Valluri R. Rao ,  Paul B. Fischer ,  Robert S. Chau

IPC: H01L31/0312 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/20 ,  H01L21/36 ,  H01L25/18 ,  H01L23/00 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065

Abstract: The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.

公开(公告)号：US10672831B2

公开(公告)日：2020-06-02

申请号：US16594595

申请日：2019-10-07

Applicant: Intel Corporation

Inventor： Yih Wang ,  Patrick Morrow

IPC: H01L27/24 ,  H01L43/08 ,  H01L27/22 ,  H01L45/00 ,  H01L43/02 ,  G11C11/16 ,  G11C13/00

Abstract: A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits.

公开(公告)号：US20200152750A1

公开(公告)日：2020-05-14

申请号：US16487077

申请日：2017-03-28

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Glenn A. Glass ,  Anand S. Murthy ,  Rishabh Mehandru

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285

Abstract: Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.

公开(公告)号：US10529827B2

公开(公告)日：2020-01-07

申请号：US15748842

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Patrick Morrow ,  Paul B. Fischer ,  Aaron D. Lilak ,  Stephen M. Cea

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/8238

Abstract: Embodiments of the invention include vertically oriented long channel transistors and methods of forming such transistors. In one embodiment, a method of forming such a transistor may include forming a fin on a semiconductor substrate. Embodiments may also include forming a spacer over an upper portion of the fin and a lower portion of the fin not covered by the spacer may be exposed. Embodiments may also include forming a gate dielectric layer over the exposed portion of the fin. A gate electrode may then be deposited, according to an embodiment. Embodiments may include exposing a top portion of the fin and forming a first source/drain (S/D) region in the top portion of the fin. The second S/D region may be formed by removing the semiconductor substrate to expose a bottom portion of the fin and forming the second S/D region in the bottom portion of the fin.

公开(公告)号：US20190386661A1

公开(公告)日：2019-12-19

申请号：US15779074

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Patrick Morrow ,  Anurag Chaudhry

IPC: H03K19/00 ,  H03K19/18 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10

Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

公开(公告)号：US20190333906A1

公开(公告)日：2019-10-31

申请号：US16475085

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Anup Pancholi ,  Prashant Majhi ,  Paul B. Fischer ,  Patrick Morrow

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; a second active device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first set and the second active device, wherein the layer is to bond the one of the layers of the first set and the second active device.