公开(公告)号：US20250112100A1

公开(公告)日：2025-04-03

申请号：US18375209

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Robert May ,  Hiroki Tanaka ,  Tarek Ibrahim ,  Lilia May ,  Jason Gamba ,  Benjamin Duong ,  Brandon Marin ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: An IC die package includes first and second IC die on a first surface of a glass layer, a bridge under the first and second IC die within an opening in the glass layer, and first and second package conductive features on a second surface of the glass layer opposite the first side. First interconnects comprising solder couple the bridge with the first and second IC die. Second interconnects excluding solder couple the first and second IC die with vias extending through the glass layer to the first package conductive features. Third interconnects excluding solder couple the bridge with the second package conductive features. The bridge couples the first and second IC die with each other, and the first and second IC die with the second package conductive features. A pitch of conductive features in the first interconnects is less than a pitch of conductive features in the second interconnects.

公开(公告)号：US20250105209A1

公开(公告)日：2025-03-27

申请号：US18475373

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Gang Duan ,  Yosuke Kanaoka ,  Minglu Liu ,  Srinivas V. Pietambaram ,  Brandon C. Marin ,  Bohan Shan ,  Haobo Chen ,  Jeremy Ecton ,  Benjamin T. Duong ,  Suddhasattwa Nad

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/42 ,  H01L23/538 ,  H10B80/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.

公开(公告)号：US20250096143A1

公开(公告)日：2025-03-20

申请号：US18470668

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Tarek A. Ibrahim ,  Srinivas V. Pietambaram ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48

Abstract: A microelectronic assembly includes a bridge die embedded in a substrate. The substrate includes a doped dielectric material in a layer or region directly below the bridge die, and in a layer near an upper face of the bridge die. A cavity is formed in the upper layer of the doped dielectric material for embedding the bridge die, exposing the lower layer of the doped dielectric material. After cavity formation, a selective metallization of the lower and upper layers of the doped dielectric material is performed, providing well-aligned metal layers in the region of the bridge die and the region around the bridge die.

公开(公告)号：US20240363995A1

公开(公告)日：2024-10-31

申请号：US18306399

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Bai Nie ,  Jeremy Ecton ,  Brandon C. Marin ,  Mohammad Mamunur Rahman

IPC: H01Q1/22 ,  G06F1/16

CPC classification number: H01Q1/2283 ,  G06F1/1698

Abstract: Disclosed herein are antenna units, microelectronic assemblies, and communication devices that may enable RF chip-to-chip communications in a compact form factor. An example microelectronic assembly may include a microelectronic component (e.g., a package substrate, a circuit board, and interposer, or a die) and an antenna unit that may be separately fabricated and integrated in a recess in the microelectronic component, enabling increased degrees of design freedom and improved yield. An example antenna unit may include a glass core having a first face and an opposing second face, a tapered opening extending between the first face and the second face of the glass core, and a layer of an electrically conductive material on sidewalls of the opening, where the opening in the glass core lined with the layer of the electrically conductive material forms a horn antenna integrated in the glass core.

公开(公告)号：US20240355749A1

公开(公告)日：2024-10-24

申请号：US18756580

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Gang Duan ,  Jefferson Coker Kaplan ,  Brandon Christian Marin ,  Srinivas Venkata Ramanuja Pietambaram

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L25/16

CPC classification number: H01L23/5385 ,  H01L23/15 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/162 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Disaggregated package substrates with glass cores are disclosed. An example package substrate includes a glass core having a first side and a second side opposite the first side. The example package substrate further includes a first block of redistribution layers on the first side of the glass core. The example package substrate also includes a second block of redistribution layers on the first side of the glass core. The first block is distinct from the second block.

公开(公告)号：US12074102B2

公开(公告)日：2024-08-27

申请号：US16827085

申请日：2020-03-23

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Ravindranath Mahajan ,  Brandon Marin ,  Jeremy Ecton ,  Mohammad Mamunur Rahman

IPC: H01L23/00 ,  H01L23/50 ,  H01L23/538 ,  H01L29/06 ,  H01L23/40

CPC classification number: H01L23/50 ,  H01L23/5383 ,  H01L29/0649 ,  H01L2023/4031

Abstract: An integrated circuit package comprising an integral structural member embedded within dielectric material and at least partially surrounding a keep-out zone of a co-planar package metallization layer. The integral structural member may increase stiffness of the package without increasing the package z-height. The structural member may comprise a plurality of intersecting elements. Individual structural elements may comprise conductive vias that are non-orthogonal to a plane of the package. An angle of intersection and thickness of the structural elements may be varied to impart more or less local or global rigidity to a package according to a particular package application. Intersecting openings may be patterned in a mask material by exposing a photosensitive material through a half-penta prism. Structural material may be plated or otherwise deposited into the intersecting openings.

公开(公告)号：US20240222139A1

公开(公告)日：2024-07-04

申请号：US18090879

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Brandon Marin ,  Gang Duan ,  Jeremy Ecton ,  Srinivas Pietambaram

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/495 ,  H01L25/065

CPC classification number: H01L21/4842 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16258

Abstract: Microelectronic integrated circuit package structures include a solder joint structure having a first portion on a die and a second portion on a substrate. The first portion comprises a first metal. An inner portion of the second portion comprises a second metal, and an outer portion of the second portion comprises an intermetallic compound (IMC) of the first and second metals.

公开(公告)号：US20240222035A1

公开(公告)日：2024-07-04

申请号：US18090305

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Kristof Darmawikarta ,  Benjamin Duong ,  Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton ,  Jason Steill ,  Thomas Sounart ,  Darko Grujicic

IPC: H01G4/33 ,  H01G4/012 ,  H01G4/252 ,  H01L21/48 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01G4/33 ,  H01G4/012 ,  H01G4/252 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/165 ,  H01L23/3675

Abstract: Apparatuses, capacitor structures, assemblies, and techniques related to package substrate embedded capacitors are described. A capacitor architecture includes a multi-layer capacitor structure at least partially within an opening extending through an insulative material layer of a package substrate or on a package substrate. The multi-layer capacitor structure includes at least two capacitor dielectric layers interleaved with a plurality of conductive layers such that the capacitor dielectric layers are at least partially within the opening and one of the conductive layers are on a sidewall of the opening.

公开(公告)号：US20240219644A1

公开(公告)日：2024-07-04

申请号：US18090260

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Benjamin Duong ,  Hiroki Tanaka ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram ,  Hari Mahalingam

IPC: G02B6/35 ,  G02B6/42 ,  H01L23/498

CPC classification number: G02B6/35 ,  G02B6/4274 ,  H01L23/49816

Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.

公开(公告)号：US20240194657A1

公开(公告)日：2024-06-13

申请号：US18080152

申请日：2022-12-13

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram

IPC: H01L25/16 ,  G02B6/42 ,  H01L21/56 ,  H01L23/00 ,  H01L23/433

CPC classification number: H01L25/167 ,  G02B6/4239 ,  G02B6/4245 ,  G02B6/4257 ,  G02B6/4269 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/08 ,  H01L24/80 ,  G02B6/426 ,  H01L24/16 ,  H01L2224/08121 ,  H01L2224/08148 ,  H01L2224/16225 ,  H01L2224/80895 ,  H01L2924/1431 ,  H01L2924/182

Abstract: Apparatuses, systems, assemblies, and techniques related to integrating photonics integrated circuit devices and electronic integrated circuit devices into an assembly or module are described. An integrated module includes a photonics integrated circuit device within an opening of a glass core substrate and an electronic integrated circuit device direct bonded to the photonics integrated circuit device. An optical waveguide is within or on the glass core substrate and has a terminal end edge coupled to the photonics integrated circuit device within the opening.