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公开(公告)号：US20170264325A1
公开(公告)日：2017-09-14
申请号：US15609946
申请日：2017-05-31
Applicant: Maxlinear, Inc.
Inventor： Subramanian Anantharaman Chandrasekarapuram , Anand Anandakumar , Stephane Laurent-Michel , Sheng Ye , Raja Pullela , Glenn Chang , Vamsi Paidi
IPC: H04B1/10
CPC classification number: H04B1/1027
Abstract: A system comprises a microwave backhaul outdoor unit having a first resonant circuit, phase error determination circuitry, and phase error compensation circuitry. The first resonant circuit is operable to generate a first signal characterized by a first amount of phase noise and a first amount of temperature stability. The phase error determination circuitry is operable to generate a phase error signal indicative of phase error between the first signal and a second signal, wherein the second signal is characterized by a second amount of phase noise that is greater than the first amount of phase noise, and the second signal is characterized by a second amount of temperature instability that is less than the first amount of temperature instability. The phase error compensation circuitry is operable to adjust the phase of a data signal based on the phase error signal, the adjustment resulting in a phase compensated signal.
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公开(公告)号：US09685983B2
公开(公告)日：2017-06-20
申请号：US14976529
申请日：2015-12-21
Applicant: Maxlinear, Inc.
Inventor： Subramanian Anantharaman Chandrasekarapuram , Anand Anandakumar , Stephane Laurent-Michel , Sheng Ye , Raja Pullela , Glenn Chang , Vamsi Paidi
CPC classification number: H04B1/1027
Abstract: A system comprises a microwave backhaul outdoor unit having a first resonant circuit, phase error determination circuitry, and phase error compensation circuitry. The first resonant circuit is operable to generate a first signal characterized by a first amount of phase noise and a first amount of temperature stability. The phase error determination circuitry is operable to generate a phase error signal indicative of phase error between the first signal and a second signal, wherein the second signal is characterized by a second amount of phase noise that is greater than the first amount of phase noise, and the second signal is characterized by a second amount of temperature instability that is less than the first amount of temperature instability. The phase error compensation circuitry is operable to adjust the phase of a data signal based on the phase error signal, the adjustment resulting in a phase compensated signal.
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公开(公告)号：US20170134032A1
公开(公告)日：2017-05-11
申请号：US15230735
申请日：2016-08-08
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
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公开(公告)号：US20170077934A1
公开(公告)日：2017-03-16
申请号：US15363762
申请日：2016-11-29
Applicant: MaxLinear, Inc.
Inventor： Sheng Ye
CPC classification number: H03L7/093 , H03L7/08 , H03L7/085 , H03L7/0891 , H03L7/18 , H03L2207/10
Abstract: A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. A sampled loop filter (SLPF) in the phase locked loop may capture charge from a charge pump (CHP) in the phase locked loop and the charge is captured at a frequency corresponding to the frequency of the reference clock signal. Opening a switch of the SLPF may hold the captured charge during a phase comparison and closing the switch may release the captured charge. The switch is controlled utilizing a control signal. By utilizing the SLPF in the phase locked loop, the phase locked loop may eliminate, at an output of the CHP, disturbance which is associated with duty cycle errors of the crystal clock signal.
Abstract translation: 锁相环可以用于利用倍频器产生频率为晶体时钟信号频率的两倍的参考时钟信号，并被键入晶体时钟信号的上升沿和下降沿。 锁相环中的采样环路滤波器（SLPF）可以在锁相环中从电荷泵（CHP）捕获电荷，并以与参考时钟信号的频率对应的频率捕获电荷。 打开SLPF的开关可能会在相位比较期间保持捕获的电荷，并且关闭开关可能会释放捕获的电荷。 利用控制信号控制开关。 通过在锁相环中使用SLPF，锁相环可以在CHP的输出处消除与晶体时钟信号的占空比误差相关的干扰。
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75.发明授权Method and system for asynchronous successive approximation analog-to-digital convertor (ADC) architecture 有权异步逐次逼近模数转换器（ADC）架构的方法和系统公开(公告)号：US09537503B2
公开(公告)日：2017-01-03
申请号：US15151042
申请日：2016-05-10
Applicant: MaxLinear, Inc.
Inventor： Xuefeng Chen , Kok Lim Chan , Eric Fogleman , Sheng Ye
CPC classification number: H03M1/38 , H03M1/06 , H03M1/0682 , H03M1/125 , H03M1/466
Abstract: Systems and methods are provided for detecting meta-stability during processing of signals. A meta-stability detector may comprise a timing control circuit, a plurality of signal adjustment circuits, and a plurality of signal state circuits. The timing control circuit may measure comparison time for each conversion cycle during analog-to-digital conversions. Each signal adjustment circuit may apply a logical operation to one or more input signals to the signal adjustment circuit, and provide a corresponding output signal. Each signal state circuit may store state information relating to one or more input signals to the signal state circuit, for at least one processing cycle; and provide an output signal based on prior stored information. The plurality of signal state circuits, plurality of signal adjustment circuits, and the timing control circuit may be arranged to generate one or more control signals for controlling an analog-to-digital converter (ADC) during the analog-to-digital conversions.
Abstract translation: 提供了用于在信号处理期间检测元稳定性的系统和方法。 元稳定性检测器可以包括定时控制电路，多个信号调整电路和多个信号状态电路。 定时控制电路可以测量模数转换期间每个转换周期的比较时间。 每个信号调整电路可以向信号调整电路的一个或多个输入信号施加逻辑运算，并提供对应的输出信号。 至少一个处理周期，每个信号状态电路可以将与一个或多个输入信号有关的状态信息存储到信号状态电路; 并基于先前存储的信息提供输出信号。 多个信号状态电路，多个信号调节电路和定时控制电路可以被布置成在模数转换期间产生用于控制模数转换器（ADC）的一个或多个控制信号。
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Patent Agency Ranking
76.发明授权Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCS) 有权异步逐次逼近寄存器（SAR）模数转换器（ADCS）的方法和系统公开(公告)号：US09413378B2
公开(公告)日：2016-08-09
申请号：US14843445
申请日：2015-09-02
Applicant: MaxLinear, Inc.
Inventor： Eric Fogleman , Sheng Ye , Xuefeng Chen , Kok Lim Chan
Abstract: Methods and systems are provided for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs) that utilize preemptive bit setting decisions. In particular, such SAR ADC may be operable to, when a failure to determine a valid output decision for each comparison step occurs, set one or more remaining bits, up to but not including one or more overlapping redundant bits in a code word corresponding to the comparison step, to a particular value. The value may be derived from a value of a bit determined in an immediately preceding decision. The failure may be determined based on dynamic and/or adaptive criteria. The criteria may be set, e.g., so as to guarantee that a magnitude of a difference between an analog input voltage to the SAR ADC and analog output voltage of a digital-to-analog converter (DAC) used therein is within overlapping ranges of voltages corresponding to the overlapping redundant bits.
Abstract translation: 提供了利用抢占位设置决定的异步逐次逼近寄存器（SAR）模数转换器（ADC）的方法和系统。 特别地，这样的SAR ADC可以可操作用于当发生针对每个比较步骤确定有效输出判定的故障时，设置一个或多个剩余的位，直到但不包括一个或多个重叠的冗余位在对应于 比较步骤，到一个特定的价值。 该值可以从紧接在前的判定中确定的比特的值导出。 可以基于动态和/或适应性标准来确定故障。 可以设置标准，例如，以便确保SAR模拟输入电压与其中使用的数模转换器（DAC）的模拟输出电压之间的差异幅度在电压的重叠范围内 对应于重叠的冗余位。
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公开(公告)号：US20160134921A1
公开(公告)日：2016-05-12
申请号：US14988338
申请日：2016-01-05
Applicant: MaxLinear, Inc.
Inventor： Anand Anandakumar , Sheng Ye , Curtis Ling
IPC: H04N21/426 , H04N21/61 , H04N21/443 , H04N21/462 , H04N5/50 , H04N21/438
CPC classification number: H04N21/4263 , H04N5/44 , H04N5/50 , H04N21/4383 , H04N21/4436 , H04N21/4622 , H04N21/6143
Abstract: Methods and systems for multi-path video and network channels may comprise a communication device comprising a wideband path (WB) and a narrowband path (NB). A video channel and a network channel may be received in the WB when the device is operating in a first stage. A video channel and a network channel may be received in the WB and the network channel may also be received in the NB when the device is operating in a second stage. The network channel may be received in the NB when the device is operating in a third stage. The reception of the network channel from both the WB and NB may enable a continuous reception of the network channel in a transition between the first and third stages. The WB may be operable to receive a plurality of channels and the NB may be operable to receive a single channel.
Abstract translation: 用于多路径视频和网络信道的方法和系统可以包括包括宽带路径（WB）和窄带路径（NB）的通信设备。 当设备在第一阶段中操作时，可以在WB中接收视频信道和网络信道。 在WB中可以接收视频信道和网络信道，并且当设备在第二阶段中操作时，也可以在NB中接收网络信道。 当设备在第三阶段中操作时，可以在NB中接收网络信道。 来自WB和NB的网络信道的接收可以在第一和第三阶段之间的转变中实现网络信道的连续接收。 WB可以用于接收多个信道，并且NB可以用于接收单个信道。
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公开(公告)号：US20160128136A1
公开(公告)日：2016-05-05
申请号：US14929465
申请日：2015-11-02
Applicant: MaxLinear, Inc.
Inventor： Anand Anandakumar , Sheng Ye , Stephane Laurent-Michel , Glenn Chang , Raja Pullela , Vamsi Paidi
IPC: H04W88/08
CPC classification number: H04L27/0014 , H04L2027/0067
Abstract: A system comprises a microwave backhaul outdoor unit having a first resonant circuit, phase error determination circuitry, and phase error compensation circuitry. The first resonant circuit is operable to generate a first signal characterized by a first amount of phase noise and a first amount of temperature stability. The phase error determination circuitry is operable to generate a phase error signal indicative of phase error between the first signal and a second signal, wherein the second signal is characterized by a second amount of phase noise that is greater than the first amount of phase noise, and the second signal is characterized by a second amount of temperature instability that is less than the first amount of temperature instability. The phase error compensation circuitry is operable to adjust the phase of a data signal based on the phase error signal, the adjustment resulting in a phase compensated signal.
Abstract translation: 一种系统包括具有第一谐振电路，相位误差确定电路和相位误差补偿电路的微波回程室外单元。 第一谐振电路可操作以产生第一信号，其特征在于第一量相位噪声和第一量度的温度稳定性。 相位误差确定电路可操作以产生指示第一信号和第二信号之间的相位误差的相位误差信号，其中第二信号的特征在于大于第一相位噪声量的第二相位噪声量， 并且第二信号的特征在于小于第一温度不稳定性的第二量的温度不稳定性。 相位误差补偿电路可操作以基于相位误差信号调整数据信号的相位，导致相位补偿信号的调整。
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公开(公告)号：US20160112081A1
公开(公告)日：2016-04-21
申请号：US14918793
申请日：2015-10-21
Applicant: Maxlinear, Inc.
Inventor： Curtis Ling , Sheng Ye
CPC classification number: H04B1/30 , H03F3/24 , H04B1/0007 , H04B2001/0408
Abstract: A transceiver comprises local oscillator circuitry, phase noise determination circuitry, mixing circuitry, and digital signal processing circuitry. The local oscillator circuitry is operable to generate a local oscillator signal. The phase noise determination circuitry is operable to introduce a frequency-dependent phase shift to the local oscillator signal to generate a phase-shifted version of the local oscillator signal. The mixing circuitry is operable to mix the local oscillator signal and the phase-shifted version of the local oscillator to generate a baseband signal having an amplitude proportional to a phase difference between the local oscillator signal and the phase-shifted version of the local oscillator signal. The digital signal processing circuity is operable to process the baseband signal to determine a phase error of the local oscillator signal, and perform signal compensation based on the determined phase error.
Abstract translation: 收发器包括本地振荡器电路，相位噪声确定电路，混合电路和数字信号处理电路。 本地振荡器电路可操作以产生本地振荡器信号。 相位噪声确定电路可操作以将频率相关相移引入本地振荡器信号以产生本地振荡器信号的相移版本。 混合电路可操作以将本地振荡器信号和本地振荡器的相移版本混合以产生具有与本地振荡器信号和本地振荡器信号的相移版本之间的相位差成比例的幅度的基带信号 。 数字信号处理电路可操作来处理基带信号以确定本地振荡器信号的相位误差，并且基于确定的相位误差执行信号补偿。
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公开(公告)号：US20160013801A1
公开(公告)日：2016-01-14
申请号：US14860262
申请日：2015-09-21
Applicant: MaxLinear, Inc.
Inventor： Sheng Ye
CPC classification number: H03L7/093 , H03L7/08 , H03L7/085 , H03L7/0891 , H03L7/18 , H03L2207/10
Abstract: A phase locked loop may be operable to generate, utilizing a frequency doubler, a reference clock signal whose frequency is twice a frequency of a crystal clock signal and is keyed on both rising and falling edges of the crystal clock signal. A sampled loop filter (SLPF) in the phase locked loop may capture charge from a charge pump (CHP) in the phase locked loop and the charge is captured at a frequency corresponding to the frequency of the reference clock signal. A switch of the sampled loop filter is utilized and controlled to manage holding and releasing of the captured charge, where the switch is controlled utilizing a control signal. By utilizing the sampled loop filter in the phase locked loop, the phase locked loop may eliminate, at an output of the charge pump, disturbance which is associated with duty cycle errors of the crystal clock signal.
Abstract translation: 锁相环可以用于利用倍频器产生频率为晶体时钟信号频率的两倍的参考时钟信号，并被键入晶体时钟信号的上升沿和下降沿。 锁相环中的采样环路滤波器（SLPF）可以在锁相环中从电荷泵（CHP）捕获电荷，并以与参考时钟信号的频率对应的频率捕获电荷。 利用和控制采样环路滤波器的开关来管理捕获的电荷的保持和释放，其中使用控制信号来控制开关。 通过在锁相环中利用采样环路滤波器，锁相环可以在电荷泵的输出处消除与晶体时钟信号的占空比误差相关的干扰。
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