公开(公告)号：US20200243557A1

公开(公告)日：2020-07-30

申请号：US16843714

申请日：2020-04-08

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Qiang XU ,  Fandong LIU ,  Zongliang HUO ,  Zhiliang XIA ,  Yaohua YANG ,  Peizhen HONG ,  Wenyu HUA ,  Jia HE

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/08 ,  H01L29/10

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the method comprises: providing a substrate; forming an alternating stack over the substrate, the alternating stack comprising a plurality of tiers of sacrificial layer/insulating layer pairs extending along a first direction substantially parallel to a top surface of the substrate; forming a plurality of tiers of word lines extending along the first direction based on the alternating stack; forming at least one connection portion conductively connecting two or more of the word lines of the plurality of tiers of word lines; and forming at least one metal contact via conductively shared by connected word lines, the at least one metal contact via being connected to at least one metal interconnect.

公开(公告)号：US20190013326A1

公开(公告)日：2019-01-10

申请号：US16046299

申请日：2018-07-26

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Wenyu HUA ,  Zhiliang XIA ,  Yangbo JIANG ,  Fandong LIU ,  Peizhen HONG ,  Fenghua FU ,  Yaohua YANG ,  Ming ZENG ,  Zongliang HUO

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28

Abstract: The present disclosure describes methods and structures for three-dimensional memory devices. The methods include providing a bottom substrate and forming a plurality of doped layers over the bottom substrate. The plurality of doped layers has a total thickness in a thickness range such that a top surface of the plurality of doped layers is substantially flat and a doping concentration of each of the plurality of doped layers is substantially uniform along a direction substantially perpendicular to the top surface of the plurality of doped layers.

公开(公告)号：US20250120086A1

公开(公告)日：2025-04-10

申请号：US18987845

申请日：2024-12-19

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhong ZHANG ,  Zhongwang SUN ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zhi ZHANG

IPC: H10B43/27 ,  G11C16/08 ,  H10B43/10 ,  H10B43/40

Abstract: A semiconductor device includes a stack including word line layers and insulating layers that are alternatingly stacked, a first block including a first staircase positioned in the stack that extends between first array regions, a second block including a second staircase positioned in the stack that extends between second array regions, a connection region positioned in the stack, wherein the first array regions and the first staircase are positioned at a first side of the connection region, and the second array regions and the second staircase are positioned at a second side of the connection region, and a slit structure positioned in the connection region between the first staircase and the second staircase. The slit structure includes a dielectric material and divides the connection region into a first portion and a second portion.

公开(公告)号：US20250056801A1

公开(公告)日：2025-02-13

申请号：US18929113

申请日：2024-10-28

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhong ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A semiconductor device includes a stack including gate layers and insulating layers alternately stacked along a first direction, channel structures located in an array region of the stack, a first staircase located at a first section in a connection region of the stack, the connection region and the array region arranged in a second direction perpendicular to the first direction, a second staircase located at a second section in the connection region of the stack, and an intermediate staircase located at the first section and disposed between the first staircase and the second staircase in the second direction. The intermediate staircase includes intermediate group stair steps ascending in the second direction. The intermediate staircase has a first sidewall and a second sidewall in the second direction. The second sidewall is closer to the second staircase than the first sidewall. The second sidewall is parallel to the first direction. The intermediate group stair steps of the intermediate staircase face the first staircase.

公开(公告)号：US20250029972A1

公开(公告)日：2025-01-23

申请号：US18905477

申请日：2024-10-03

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Kun ZHANG ,  Linchun WU ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: In an example, a three-dimensional (3D) memory device includes a stack structure including interleaved conductive layers and dielectric layers, a first semiconductor layer above the stack structure, a second semiconductor layer above the first semiconductor layer, channel structures extending vertically through the stack structure and the first semiconductor layer, and a source contact in contact with the second semiconductor layer.

公开(公告)号：US20240389307A1

公开(公告)日：2024-11-21

申请号：US18458563

申请日：2023-08-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Dongxue ZHAO ,  Yuhui HAN ,  Di WANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: H10B12/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: Examples of the present disclosure disclose a fabrication method of a semiconductor device, a semiconductor device and a memory system. The method includes: providing a stack structure including a device region and a connection region arranged in a first direction, the stack structure including an interlayer insulating layer and a composite material layer alternatively stacked in a second direction, the composite material layer including a bit line in the connection region, and the second direction intersecting the first direction; forming a contact hole in the connection region, the contact hole extending to the bit line from a first side of the stack structure in the second direction; and forming a contact structure connected with bit line in the contact hole.

公开(公告)号：US20240251558A1

公开(公告)日：2024-07-25

申请号：US18624578

申请日：2024-04-02

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhong ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: In one aspect, a three-dimensional (3D) memory device includes a first core region, a second core region, and an isolation region between the first and second core regions along a first direction, a stack in the first and second core regions and including alternatingly stacked first dielectric layers and conductor layers, gate line slit structures extending through the stack along a second direction perpendicular to the first direction in the first and second core regions, top select gate (TSG) cut structures extending through a portion of the stack along the second direction, and a first isolation structure extending through the stack along the second direction in the isolation region and contacting with the gate line slit structures. The gate line slit structures and the TSG cut structures extend along the first direction. One of the TSG cut structures is between two of the gate line slit structures along a third direction perpendicular to the first direction and the second direction.

公开(公告)号：US20240188290A1

公开(公告)日：2024-06-06

申请号：US18082048

申请日：2022-12-15

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Wei XIE ,  Dongyu FAN ,  Di WANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: H10B43/20 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792

CPC classification number: H10B43/20 ,  H01L29/40117 ,  H01L29/42348 ,  H01L29/7926

Abstract: Memory device and formation method are provided. The memory device includes a stack structure; and a plurality of gate line slit structures vertically extending through the stack structure to divide the stack structure into a plurality of stack portions. The plurality of GLS structures extend along a first direction in a lateral plane of the stack structure and are arranged along a second direction substantially perpendicular to the first direction. Each stack portion is between corresponding adjacent gate line slit structures. At least one edge stack portion, along the second direction of the plurality of stack portions at edge of the stack structure includes a configuration different from a non-edge stack portion of the plurality of stack portions along the second direction.

公开(公告)号：US20240164105A1

公开(公告)日：2024-05-16

申请号：US18090142

申请日：2022-12-28

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Tao YANG ,  Dongxue ZHAO ,  Wenxi ZHOU ,  Zhiliang XIA

IPC: H10B43/35 ,  G11C16/04 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

Abstract: A memory, a controlling method thereof, a memory system and an electronic device are disclosed. The memory can include a semiconductor layer and a memory array disposed on the semiconductor layer. The memory array can include a plurality of memory strings connected with the same bit line. Each memory string can include a memory cell and a select cell connected on at least one side of the memory cell. The select cell can include a first kind of transistors with a first threshold voltage and a second kind of transistors with a second threshold voltage. The first kind of transistors can be connected with the second kind of transistors. The first threshold voltage can be different from the second threshold voltage. Different memory strings can be controlled to be on or off to realize selective controlling functions for a plurality of memory strings connected with the same bit line.

公开(公告)号：US20240105266A1

公开(公告)日：2024-03-28

申请号：US17950931

申请日：2022-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Tao YANG ,  Dongxue ZHAO ,  Lei LIU ,  Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.