公开(公告)号：US20140264475A1

公开(公告)日：2014-09-18

申请号：US13925127

申请日：2013-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rueijer Lin ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00158 ,  B81B7/008 ,  B81B2207/015 ,  B81B2207/096 ,  B81C1/00246 ,  B81C1/00333 ,  B81C1/00539 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/0127 ,  B81C2203/0742 ,  B81C2203/0778 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02247 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802

Abstract: An integrated circuit device includes a dielectric layer disposed over a semiconductor substrate, the dielectric layer having a sacrificial cavity formed therein, a membrane layer formed onto the dielectric layer, and a capping structure formed on the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer.

Abstract translation: 一种集成电路器件，包括设置在半导体衬底上的电介质层，介电层具有形成在其中的牺牲腔，形成在电介质层上的膜层，以及形成在膜层上的封盖结构，从而形成第二腔， 第二腔通过形成于膜层中的通孔连接到牺牲腔。

公开(公告)号：US08791021B2

公开(公告)日：2014-07-29

申请号：US13409868

申请日：2012-03-01

Applicant: Mohamed Serry ,  Andrew Rubin ,  Mohamed Refaat ,  Sherif Sedky ,  Mohammad Abdo

Inventor： Mohamed Serry ,  Andrew Rubin ,  Mohamed Refaat ,  Sherif Sedky ,  Mohammad Abdo

IPC: H01L21/311

CPC classification number: H01L21/3081 ,  B81C1/00396 ,  B81C2201/0132 ,  H01L21/3065 ,  H01L21/76898

Abstract: Polycrystalline silicon germanium (SiGe) can offer excellent etch selectivity to silicon during cryogenic deep reactive ion etching in an SF6/O2 plasma. Etch selectivity of over 800:1 (Si:SiGe) may be achieved at etch temperatures from −80 degrees Celsius to −140 degrees Celsius. High aspect ratio structures with high resolution may be patterned into Si substrates using SiGe as a hard mask layer for construction of microelectromechanical systems (MEMS) devices and semiconductor devices.

Abstract translation: 在SF6 / O2等离子体的低温深反应离子蚀刻中，多晶硅锗（SiGe）可以提供优异的硅蚀刻选择性。 在-80摄氏度至-140摄氏度的蚀刻温度下，可获得超过800：1（Si：SiGe）的蚀刻选择性。 可以使用SiGe作为用于构建微机电系统（MEMS）器件和半导体器件的硬掩模层来将具有高分辨率的高纵横比结构图案化为Si衬底。

公开(公告)号：US20140131707A1

公开(公告)日：2014-05-15

申请号：US14110128

申请日：2012-11-12

Applicant: Fuji Electric Co., Ltd.

Inventor： Hiroshi Tomizawa ,  Takuya Furuichi

IPC: H01L21/66

CPC classification number: H01L22/14 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00563 ,  B81C2201/0132 ,  H01L22/26 ,  H01L22/30

Abstract: Provide is an etching completion detection method that accurately detects an etching completion position in an SOI substrate, regardless of the width of an opening. This etching completion detection method is a method for detecting etching completion when a silicon layer is being etched to form an opening that reaches an insulating layer in an SOI substrate in which the silicon layer is disposed on the insulating layer, the method including: forming a first electrode layer on a surface of an islet region that is surrounded by a loop-shaped opening to be formed by the etching, and a second electrode layer in a region outside the stripe region; measuring an electrical resistance between the first electrode layer and the second electrode layer; and determining that the loop-shaped opening has reached an etching completion position when the electrical resistance exceeds a preset threshold.

Abstract translation: 提供一种蚀刻完成检测方法，其能够准确地检测SOI衬底中的蚀刻完成位置，而与开口的宽度无关。 这种蚀刻完成检测方法是当硅层被蚀刻以形成在绝缘层上设置硅层的SOI衬底中到达绝缘层的开口时检测蚀刻完成的方法，该方法包括：形成 由被蚀刻形成的环形开口包围的胰岛区域的表面上的第一电极层和在条带区域外的区域中的第二电极层; 测量第一电极层和第二电极层之间的电阻; 并且当电阻超过预设阈值时，确定环形开口已经达到蚀刻完成位置。

公开(公告)号：US08659099B2

公开(公告)日：2014-02-25

申请号：US13586576

申请日：2012-08-15

Applicant: Jochen Reinmuth ,  Heribert Weber

Inventor： Jochen Reinmuth ,  Heribert Weber

IPC: H01L29/84

CPC classification number: G01P15/0802 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00626 ,  B81C2201/0132 ,  B81C2203/0136 ,  G01C19/5783

Abstract: A method for manufacturing a micromechanical structure includes: forming a first insulation layer above a substrate; forming a first micromechanical functional layer on the first insulation layer; forming multiple first trenches in the first micromechanical functional layer, which trenches extend as far as the first insulation layer; forming a second insulation layer on the first micromechanical functional layer, which second insulation layer fills up the first trenches; forming etch accesses in the second insulation layer, which etch accesses locally expose the first micromechanical functional layer; and etching the first micromechanical functional layer through the etch accesses, the filled first trenches and the first insulation layer acting as an etch stop.

Abstract translation: 一种制造微机械结构的方法包括：在基板上形成第一绝缘层; 在所述第一绝缘层上形成第一微机械功能层; 在所述第一微机械功能层中形成多个第一沟槽，所述沟槽延伸到所述第一绝缘层; 在所述第一微机械功能层上形成第二绝缘层，所述第二绝缘层填充所述第一沟槽; 在所述第二绝缘层中形成蚀刻访问，所述蚀刻访问局部暴露所述第一微机械功能层; 并且通过蚀刻访问蚀刻第一微机械功能层，填充的第一沟槽和用作蚀刻停止层的第一绝缘层。

公开(公告)号：US08652343B2

公开(公告)日：2014-02-18

申请号：US10524525

申请日：2003-08-14

Applicant: Martin Hausner

Inventor： Martin Hausner

IPC: B44C1/22 ,  H01L21/302

CPC classification number: H01L21/3065 ,  B81C1/00626 ,  B81C2201/0132 ,  B81C2201/0142 ,  H01L21/30655 ,  H01L21/3081

Abstract: A method for the selective removal of material from a substrate surface for forming a deepening includes the steps of applying a mask onto the substrate surface in accordance with the desired selective removal and dry-etching the substrate, a metal, preferably aluminum, being used as the masking material. Power may be coupled inductively to a plasma.

Abstract translation: 用于从衬底表面选择性地去除用于形成深化的方法包括以下步骤：根据期望的选择性去除和干蚀刻衬底，金属，优选铝，将掩模施加到衬底表面上，用作 掩蔽材料。 功率可以感应耦合到等离子体。

公开(公告)号：US08501029B2

公开(公告)日：2013-08-06

申请号：US11554537

申请日：2006-10-30

Applicant: Timothy Beerling ,  Hongfeng Yin

Inventor： Timothy Beerling ,  Hongfeng Yin

IPC: C23F1/00

CPC classification number: B81C1/00063 ,  B01L3/5027 ,  B81B2201/058 ,  B81C2201/0132 ,  G01N30/6095

Abstract: In accordance with the invention, a method for making microfluidic structures in bulk titanium is disclosed. Specific microfluidic structures include HPLC structures.

Abstract translation: 根据本发明，公开了一种在体积钛中制造微流体结构的方法。 特定的微流体结构包括HPLC结构。

公开(公告)号：US20130183773A1

公开(公告)日：2013-07-18

申请号：US13731296

申请日：2012-12-31

Applicant: Amy M. Tseng ,  Brian V. Jenkins ,  Robert Mack

Inventor： Amy M. Tseng ,  Brian V. Jenkins ,  Robert Mack

IPC: G01N31/22

CPC classification number: G01N31/221 ,  B81C1/00531 ,  B81C2201/0132 ,  B81C2201/0142 ,  C09K13/00 ,  G01N21/272 ,  G01N21/80 ,  G01N35/085 ,  G01N2021/8411 ,  G01N2021/8557 ,  H01L21/67063 ,  H01L22/12 ,  Y10T436/153333

Abstract: The invention is directed towards methods and compositions for identifying the amount of hydrofluoric acid in a buffered oxide etching composition. In buffered oxide etching compositions it is very difficult to measure the amount of hydrofluoric acid because it has varying equilibriums and it is toxic so it hard to handle and sample. When used to manufacture microchips however, incorrect amounts of hydrofluoric acid will ruin those chips. The invention utilizes a unique method of spectrographically measuring the hydrofluoric acid when in contact with added chromogenic agents to obtain exact measurements that are accurate, immediate, and safe.

Abstract translation: 本发明涉及用于鉴定缓冲氧化物蚀刻组合物中氢氟酸的量的方法和组合物。 在缓冲氧化物蚀刻组合物中，非常难以测量氢氟酸的量，因为其具有不同的平衡，并且它是有毒的，因此难以处理和取样。 然而，当用于制造微芯片时，不正确量的氢氟酸会破坏这些芯片。 当与添加的显色剂接触时，本发明利用光谱测量氢氟酸的独特方法，以获得准确，立即和安全的精确测量。

公开(公告)号：US20130025322A1

公开(公告)日：2013-01-31

申请号：US13446053

申请日：2012-04-13

Applicant: Hyungryul Choi ,  Chih-Hao Chang ,  Kyoo Chul Park ,  Gareth H. McKinley ,  George Barbastathis ,  Jeong-gil Kim

Inventor： Hyungryul Choi ,  Chih-Hao Chang ,  Kyoo Chul Park ,  Gareth H. McKinley ,  George Barbastathis ,  Jeong-gil Kim

IPC: C03C15/00 ,  C03B13/16 ,  C03B13/08

CPC classification number: B81C1/00111 ,  B81C1/00103 ,  B81C2201/0132

Abstract: Fabrication method. At least first and second hardmasks are deposited on a substrate, the thickness and materials of the first and second hardmask selected to provided etch selectivity with respect to the substrate. A nanoscale pattern of photoresist is created on the first hardmask and the hardmask is etched through to create the nanoscale pattern on a second hardmask. The second hardmask is etched through to create the desired taper nanocone structures in the substrate. Reactive ion etching is preferred. A glass manufacturing process using a roller imprint module is also disclosed.

Abstract translation: 制作方法。 至少第一和第二硬掩模沉积在衬底上，第一和第二硬掩模的厚度和材料被选择为提供相对于衬底的蚀刻选择性。 在第一硬掩模上形成光刻胶的纳米尺度图案，并且硬掩模被蚀刻穿过以在第二硬掩模上产生纳米尺度图案。 蚀刻第二个硬掩模，以在衬底中产生所需的锥形纳米结构。 反应离子蚀刻是优选的。 还公开了使用辊压印模块的玻璃制造工艺。

公开(公告)号：US20110115042A1

公开(公告)日：2011-05-19

申请号：US13005767

申请日：2011-01-13

Applicant: André Paul Labonté ,  Lee James Jacobson

Inventor： André Paul Labonté ,  Lee James Jacobson

IPC: H01L31/0232

CPC classification number: B81C1/00547 ,  B81C2201/0132 ,  H01L27/14625 ,  H01L27/14685

Abstract: A structure for decreasing minimum feature size in an integrated circuit design that includes a substrate comprising a first material is provided. The structure comprises a layer of second material formed on a surface of the substrate and a micro-aperture formed in the layer of second material. The micro-aperture has sidewalls formed to be substantially perpendicular to the surface of the substrate and a horizontal tip formed on the surface of the substrate and extending orthogonally from a portion of the sidewalls.

Abstract translation: 提供了一种用于降低集成电路设计中的最小特征尺寸的结构，其包括包括第一材料的基板。 该结构包括形成在基板的表面上的第二材料层和形成在第二材料层中的微孔。 微孔具有形成为基本上垂直于衬底的表面的侧壁和形成在衬底的表面上并从侧壁的一部分正交延伸的水平尖端。

公开(公告)号：US07897510B2

公开(公告)日：2011-03-01

申请号：US11896009

申请日：2007-08-29

Applicant: Kei Murayama ,  Akinori Shiraishi ,  Masahiro Sunohara ,  Yuichi Taguchi ,  Naoyuki Koizumi ,  Mitsutoshi Higashi

Inventor： Kei Murayama ,  Akinori Shiraishi ,  Masahiro Sunohara ,  Yuichi Taguchi ,  Naoyuki Koizumi ,  Mitsutoshi Higashi

IPC: H01L21/00

CPC classification number: H01L23/055 ,  B81B7/007 ,  B81B2203/0353 ,  B81B2203/0384 ,  B81B2207/096 ,  B81C1/00103 ,  B81C2201/0132 ,  H01L21/486 ,  H01L23/13 ,  H01L23/147 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method for manufacturing a package which includes: an etching step of etching a silicon substrate, and forming a via hole penetrating through the silicon substrate; and a step of embedding an electrically conductive material in the via hole, and forming a via plug, characterized in that the etching step includes a first etching step of forming the via hole in a straight shape, and a second etching step of forming the via hole in a taper shape.

Abstract translation: 一种制造封装的方法，包括：蚀刻步骤，蚀刻硅衬底，以及形成穿透硅衬底的通孔; 以及在所述通孔中嵌入导电材料的步骤，以及形成通孔塞，其特征在于，所述蚀刻步骤包括以直线形状形成所述通孔的第一蚀刻步骤和形成所述通孔的第二蚀刻步骤 孔呈锥形。