公开(公告)号：US20230195645A1

公开(公告)日：2023-06-22

申请号：US17556431

申请日：2021-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SOORAJ PUTHOOR ,  MUHAMMAD AMBER HASSAAN ,  ASHWIN AJI ,  MICHAEL L. CHU ,  NUWAN JAYASENA

IPC: G06F12/1009 ,  G06F12/1045 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F12/1009 ,  G06F12/1054 ,  G06F12/1063 ,  G06F12/0238 ,  G06F13/1673 ,  G06F2212/7201

Abstract: Process isolation for a PIM device includes: receiving, from a process, a call to allocate a virtual address space where the process stores a PIM configuration context; allocating the virtual address space including mapping a physical address space including PIM device configuration registers to the virtual address space only if the physical address space is not mapped to another process's virtual address space; and programming the PIM device configuration space according to the configuration context. When a PIM command is executed, a translation mechanism determines whether there is a valid mapping of a virtual address of the PIM command to a physical address of a PIM resource, such as a LIS entry. If a valid mapping exists, the translation is completed and the resource is accessed, but if there is not a valid mapping, the translation fails and the process is blocked from accessing the PIM resource.

公开(公告)号：US11681553B2

公开(公告)日：2023-06-20

申请号：US16562623

申请日：2019-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hanmin Cho ,  Suengchul Ryu ,  Junghyun Hong

IPC: G06F12/02 ,  G06F9/50 ,  G06F13/16 ,  G06N3/06

CPC classification number: G06F9/5016 ,  G06F9/5027 ,  G06F12/0207 ,  G06F13/1673 ,  G06N3/06 ,  G06F2212/657 ,  G06F2212/7201

Abstract: A storage device includes an accelerator including a first processor, and a storage controller that uses a buffer memory as a working memory and includes a second processor different in type from the first processor. The second processor is configured to establish a first communication path between the first processor and the buffer memory responsive to a request of the first processor, and the first processor is configured to access the buffer memory through the first communication path.

公开(公告)号：US20230178143A1

公开(公告)日：2023-06-08

申请号：US17540682

申请日：2021-12-02

Applicant: Western Digital Technologies, Inc.

Inventor： Atif Hussain ,  Vivek Shivhare

IPC: G11C11/408 ,  H03K19/17728 ,  G06F12/02

CPC classification number: G11C11/4087 ,  G11C11/4085 ,  H03K19/17728 ,  G06F12/0246 ,  G06F2212/7201

Abstract: A data storage device including, in one implementation, a memory device and a controller configured to configured to retrieve a plurality of physical memory addresses from a first lookup table in the non-volatile memory. Each physical memory address is a combination of a word line and a string number of the non-volatile memory and the each physical memory address has a first number of bits. The controller is further configured to generate a plurality of encoded values by encoding the plurality of physical memory addresses. Each of the plurality of encoded values has a second number of bits that is smaller than the first number of bits. The controller is further configured to store the plurality of encoded values in the first lookup table, generate a logical to encoded value look-up table with the plurality of encoded values, and store the logical to encoded value look-up table in the memory.

公开(公告)号：US11669445B2

公开(公告)日：2023-06-06

申请号：US17380064

申请日：2021-07-20

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Shi-Yao Zhao ,  Dao-Fu Wang ,  Yong-Peng Jing

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0292 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

Abstract: A method performed by a slave device to obtain a host memory address includes: inquiring a description list to obtain information of an allocated memory of a host; dividing the allocated memory into N storage spaces according to the information; using a first memory space of the N storage spaces to store a first level look-up table indicating physical addresses of the N storage spaces; dividing the first memory space into M storage spaces; storing a second level look-up table in the slave device to indicate physical addresses of the M storage spaces; inquiring the second level look-up table according to a logical address and obtaining a first index indicating a physical address of one of the M storage spaces; and inquiring the first level look-up table according to the first index and obtaining a second index indicating a physical address of one of the N storage spaces.

公开(公告)号：US11669264B2

公开(公告)日：2023-06-06

申请号：US17201004

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Yuki Sasaki ,  Shinichi Kanno

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory is configured to store an address translation table and a data map. In a case where an invalidation command for invalidating the data written in the non-volatile memory is received from the host, the controller is configured to update the address translation table and the data map based on the invalidation command. A response to the invalidation command is transmitted to the host after the address translation table is updated and before the data map is updated.

公开(公告)号：US11656801B2

公开(公告)日：2023-05-23

申请号：US17736806

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： Shanky Kumar Jain ,  Dmitri A. Yudanov

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/22 ,  G11C11/4091 ,  G06F12/0875 ,  G11C7/08 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/0893 ,  G06F12/1045 ,  G11C11/406 ,  G11C8/08 ,  G06F12/0802

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/109 ,  G11C7/1012 ,  G11C7/1063 ,  G11C8/08 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/40603 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/72 ,  G06F2212/7201

Abstract: Methods, systems, and devices related to data relocation via a cache are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In some cases, the memory device may transfer data from a first address of the memory array to the signal development cache. The memory device may transfer the data stored in the signal development cache to a second address of the memory array based on a parameter associated with the first address of the memory array satisfying a criterion for performing data relocation.

公开(公告)号：US11656793B2

公开(公告)日：2023-05-23

申请号：US17501938

申请日：2021-10-14

Applicant: SK hynix Inc.

Inventor： Soo Jin Park ,  Ji Yeun Kang ,  Won Hyoung Lee

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0246 ,  G06F2212/7201

Abstract: A memory system includes a memory device including memory blocks, and a controller configured to in response to a program request or a read request for a selected memory block among the memory blocks being received from a host, store first data to which a first logical address is allocated in a cache group, generate a first entry for the first data stored in the cache group, and in response to second data to which the first logical address is allocated being stored in the cache group after the first data is stored in the cache group, generate a second entry for the second data.

公开(公告)号：US11650759B2

公开(公告)日：2023-05-16

申请号：US17393155

申请日：2021-08-03

Applicant: Kioxia Corporation

Inventor： Andrew John Tomlin

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0871

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679 ,  G06F12/0871 ,  G06F2212/7201 ,  G06F2212/7207

Abstract: Various implementations described herein relate to systems and methods for managing metadata using an in-memory journal, including determining metadata for data, storing the metadata in an in-memory journal, detecting an imminent interruption to operations of the storage device, in response to detecting the imminent interruption, program the in-memory journal to a non-volatile memory device of the storage device, detect that the operations of the storage device are being restored, and in response to detecting that the operations of the storage device are being restored, performing metadata update. The first data is read from first original areas of a non-volatile memory. The first metadata includes a first physical address for each of first new areas of the non-volatile memory. The metadata is programmed in a metadata area of the non-volatile memory device.

公开(公告)号：US20190250831A1

公开(公告)日：2019-08-15

申请号：US16276449

申请日：2019-02-14

Applicant: SK hynix memory solutions America Inc.

Inventor： Seong Won SHIN ,  Yi TONG ,  Seungwan JUNG

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1024 ,  G06F2212/7201

Abstract: A data processing system includes a host device and a memory system including a plurality of units. The host device includes a workload generation component and an analysis component. The workload generation component concurrently transmits, to the memory system, a plurality of commands for the plurality of memory units. The analysis component receives, from the memory system, command completion messages corresponding to the plurality of commands; measures latencies of the plurality of commands based on the receiving of the command completion messages; and analyze a parallelism scheme of the plurality of memory units based the measured latencies.

公开(公告)号：US20190236005A1

公开(公告)日：2019-08-01

申请号：US16109070

申请日：2018-08-22

Applicant: SK hynix Inc.

Inventor： Jong-Min LEE

IPC: G06F12/02 ,  G06F3/06 ,  G06F11/14 ,  G06F11/10

CPC classification number: G06F12/0253 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0689 ,  G06F11/108 ,  G06F11/1441 ,  G06F2212/262 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7208

Abstract: A memory system includes a memory device, and a controller suitable for selecting at least one common operation necessary to be performed in first and second tasks, selecting the first or second task, and selectively performing one or more of a valid data scan operation, a valid data read operation, a valid data write operation, and a valid data map update operation based on selected information, wherein the first task is a garbage collection operation performed on a host data block, a system data block and a map data block, wherein the second task is a recovery operation performed after a sudden power-off (SPO) that occurs during the valid data map update operation.