公开(公告)号：US08000429B2

公开(公告)日：2011-08-16

申请号：US11520609

申请日：2006-09-14

Applicant: Hideo Abe ,  Yuji Obana ,  Hideaki Mochizuki

Inventor： Hideo Abe ,  Yuji Obana ,  Hideaki Mochizuki

IPC: H04L7/00

CPC classification number: H04L7/0008 ,  H04L1/205

Abstract: In a jitter correction method and circuit, combination data combined by adding, to referenced data, an end bit of data 1 clock prior to and a head bit of data 1 clock subsequent to the referenced data is sequentially generated. Each bit of the combination data is sequentially referred. When a change between a referenced bit and a bit directly adjoining the referenced bit is detected, and when a number of references reaches a multiplication number of the oversampling and a change between at least three adjoining bits including the referenced bit is not detected, change position display data regarding the directly adjoining bit as a change bit of the referenced data is generated and the number of references is initialized. When the change is not detected and the number of references does not reach the multiplication number, the number of references is incremented. All the change bits are extracted from the referenced data and the change position display data, and a data reproduction is performed corresponding to the multiplication number.

Abstract translation: 在抖动校正方法和电路中，通过将参考数据的1位时钟之后的数据的结束位和参考数据后的数据1个时钟的头位相加，结合数据组合数据。 顺序地参考组合数据的每一位。 当检测到参考位和与参考位直接相邻的位之间的变化时，并且当参考数量达到过采样的乘数并且未检测到包括参考位的至少三个相邻位之间的变化时，改变位置 生成关于直接相邻位的显示数据作为参考数据的改变位，并且引用的数量被初始化。 当未检测到变化，引用次数未达到乘数时，引用次数增加。 从参考数据和改变位置显示数据中提取所有改变位，并且对应于乘数执行数据再现。

公开(公告)号：US20110176444A1

公开(公告)日：2011-07-21

申请号：US13072954

申请日：2011-03-28

Applicant: Kousuke NOGAMI

Inventor： Kousuke NOGAMI

IPC: H04L12/26

CPC classification number: H04L1/205 ,  H04L1/004 ,  H04L1/18 ,  H04L65/80

Abstract: A transmission-time measurement section (201) and a jitter measurement section (202) measure transmission time length and jitter, respectively, by using the packets transmitted/received. A forward-error-correction (FEC)-scheme maximum-jitter measurement section (203) calculates a maximum jitter in the case of adopting an FEC scheme, and an automatic-retransmission-request (ARQ)-scheme maximum-jitter measurement section (204) calculates a maximum jitter in the case of adopting an ARQ scheme from the measured information. A packet control section (205) selects a communication scheme having a smaller maximum jitter from both schemes based on the calculation result of the FEC-maximum-jitter measurement section (203) and ARQ-maximum-jitter measurement section (204).

Abstract translation: 传输时间测量部分（201）和抖动测量部分（202）分别通过使用发送/接收的分组测量传输时间长度和抖动。 前向错误校正（FEC）最大抖动测量部（203）在采用FEC方式的情况下计算最大抖动，并且自动重发请求（ARQ） - 最大抖动测量部（ARQ） 204）根据测量信息计算采用ARQ方案的情况下的最大抖动。 分组控制部分（205）根据FEC最大抖动测量部分（203）和ARQ最大抖动测量部分（204）的计算结果从两个方案中选择具有较小最大抖动的通信方案。

公开(公告)号：US07961831B2

公开(公告)日：2011-06-14

申请号：US11729712

申请日：2007-03-29

Applicant: Adee Ran

Inventor： Adee Ran

IPC: H04L7/00

CPC classification number: H04L1/205

Abstract: In one embodiment, the present invention includes a method for receiving an incoming signal from a communication channel at a receiver, sampling the incoming signal in first and second samplers that are independently clocked, comparing outputs of the samplers, and outputting a measure of a horizontal eye opening of the incoming signal based on the comparison. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在接收机处从通信信道接收输入信号的方法，对独立计时的第一和第二采样器中的输入信号进行采样，比较采样器的输出，并输出水平测量 根据比较来打开输入信号。 描述和要求保护其他实施例。

公开(公告)号：US20110096881A1

公开(公告)日：2011-04-28

申请号：US12672482

申请日：2008-08-20

Applicant: Ruben Villarino-Villa ,  Thomas Kuhwald ,  Markus Freidhof

Inventor： Ruben Villarino-Villa ,  Thomas Kuhwald ,  Markus Freidhof

IPC: H04L7/00

CPC classification number: H04L7/0083 ,  G01R31/31709 ,  G01R31/31711 ,  H03L7/06 ,  H04L1/205 ,  H04L7/0087 ,  H04L7/0331

Abstract: A method for the recovery of a clock signal from a data signal, wherein the edges of the data signal and the clock signal are each presented by an ordered sequence of timing points, comprising determining missing edges in the sequence of data-signal edges, inserting new data-signal edges (Dx) into the sequence of data-signal edges to obtain a completed sequence of data-signal edges, and recovering the clock signal from the completed sequence of data-signal edges. The detection of missing edges in the sequence of data-signal edges is based on a prediction of the clock signal (FRONT CLOCK).

Abstract translation: 一种用于从数据信号恢复时钟信号的方法，其中数据信号和时钟信号的边缘各自由定时点的有序序列呈现，包括确定数据信号边缘序列中的丢失边缘，插入 将新的数据信号边缘（Dx）转换成数据信号边缘序列，以获得完整的数据信号边缘序列，以及从完成的数据信号边缘序列恢复时钟信号。 在数据信号边缘序列中检测到丢失边缘是基于时钟信号（FRONT CLOCK）的预测。

公开(公告)号：US07930120B2

公开(公告)日：2011-04-19

申请号：US12103689

申请日：2008-04-15

Applicant: Hayden C. Cranford, Jr. ,  Fadi H. Gebara ,  Jeremy D. Schaub

Inventor： Hayden C. Cranford, Jr. ,  Fadi H. Gebara ,  Jeremy D. Schaub

IPC: G06F19/00 ,  H04B17/00

CPC classification number: G01R31/31725 ,  G01R29/26 ,  G01R31/31709 ,  H04L1/205

Abstract: A system and circuit for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.

Abstract translation: 用于通过异步采样确定数据信号抖动的系统和电路提供了用于测量数据信号抖动的低成本和生产可集成机制。 数据信号被边缘检测并通过不相关频率的采样时钟采样，采样值根据时基上的样本的折叠而被收集在直方图中。 通过扫描确定时基以检测折叠数据的最小抖动。 正确的估计时基周期的直方图代表数据信号边缘位置的概率密度函数，抖动特性由密度函数峰的宽度和形状决定。 可以通过调整用于在整个样本集中折叠数据的时基来纠正频率漂移。

公开(公告)号：US07869544B2

公开(公告)日：2011-01-11

申请号：US11968872

申请日：2008-01-03

Applicant: Michael A. Sorna ,  William R. Kelly ,  Daniel W. Storaska

Inventor： Michael A. Sorna ,  William R. Kelly ,  Daniel W. Storaska

IPC: H04L27/00

CPC classification number: H04L1/205

Abstract: An eyewidth of a data signal is determined by steps including: (a) recovering a phase of a clock from a data signal as a sampling clock; (b) shifting the phase of the sampling clock away from the first phase by a count multiplied by predetermined phase amount; (c) sampling the data signal with the shifted sampling clock phase to obtain sample data; d) determining whether the sample data contains error; (e) when the sample data does not contain error, recovering the phase of the clock from the data signal again for use as the first phase of the sampling clock, increasing the count value and repeating steps (b) through (e); and f) when the sample data contains error, determining the eyewidth based on the last shifted phase of the sampling clock prior to determining that the sample data contains error.

Abstract translation: 数据信号的眼线宽度由以下步骤决定，包括：（a）从作为采样时钟的数据信号中恢复时钟的相位; （b）使采样时钟的相位离开第一相位移动乘以预定相位量; （c）用移位的采样时钟相位对数据信号进行采样，以获得采样数据; d）确定样本数据是否包含错误; （e）当采样数据不包含错误时，再次从数据信号中恢复时钟的相位以用作采样时钟的第一相位，增加计数值并重复步骤（b）至（e）; 以及f）当样本数据包含错误时，在确定样本数据包含错误之前，基于采样时钟的最后移位的相位来确定眼宽。

公开(公告)号：US20100329139A1

公开(公告)日：2010-12-30

申请号：US12824874

申请日：2010-06-28

Applicant: Tilo FERCHLAND ,  Michael SCHMIDT ,  Eric SACHSE

Inventor： Tilo FERCHLAND ,  Michael SCHMIDT ,  Eric SACHSE

IPC: H04J3/14

CPC classification number: H04W4/02 ,  G01S5/0289 ,  G01S13/765 ,  H04J3/0682 ,  H04L1/1848 ,  H04L1/188 ,  H04L1/205 ,  H04W56/0055 ,  H04W56/0065

Abstract: A circuit of a node in a radio network and method for transit time measurement between a first node and a second node of a radio network is provided. A frame is transmitted by the first node, wherein the frame requires an acknowledgment of reception by the second node. A first point in time of the transmission of the frame is established by the first node by a time counter. The frame is received by the second node at a second point in time. The acknowledgment is transmitted by the second node to the first node at a third point in time, wherein the third point in time depends on the second point in time by a predetermined time interval between the second point in time and the third point in time. A fourth point in time is established by the first node by the time counter when the acknowledgment is received. The transit time or the change in transit time is determined from the first point in time established by the time counter and from the established fourth point in time and from the predetermined time interval.

Abstract translation: 提供无线电网络中的节点的电路和无线电网络的第一节点和第二节点之间的传输时间测量方法。 帧由第一节点发送，其中帧需要由第二节点接收的确认。 帧的发送的第一时间点由第一节点通过时间计数器建立。 帧在第二时间点由第二节点接收。 所述确认在第三时间点由所述第二节点发送到所述第一节点，其中所述第三时间点在所述第二时间点上依赖于所述第二时间点在所述第二时间点和所述第三时间点之间的预定时间间隔。 当接收到确认时，由第一节点通过时间计数器建立第四时间点。 从通过时间计数器建立的第一时间点和从建立的第四时间点到预定的时间间隔确定通行时间或通行时间的变化。

公开(公告)号：US07844022B2

公开(公告)日：2010-11-30

申请号：US11590652

申请日：2006-10-31

Applicant: Sassan Tabatabaei

Inventor： Sassan Tabatabaei

IPC: H04L7/00

CPC classification number: G01R29/26 ,  G01R31/31709 ,  H04L1/205

Abstract: The present subject matter is directed to methodologies for measuring jitter spectral content in a sampled signal using continuous time interval analyzers (CTIA) for characterization and test of clock signals and high-speed digital interfaces. The methodology takes advantage of anti-aliasing aspects of random sampling (RS) in a time interval error (TIE) based analysis methodology by randomizing timing of samples relative to signal edges and/or intervals between signal edges.

Abstract translation: 本主题涉及使用连续时间间隔分析器（CTIA）测量采样信号中的抖动频谱含量的方法，用于表征和测试时钟信号和高速数字接口。 该方法利用基于时间间隔误差（TIE）的分析方法中的随机抽样（RS）的抗锯齿方面，通过随机化样本相对于信号边缘的时序和/或信号边缘之间的间隔。

公开(公告)号：US07839964B2

公开(公告)日：2010-11-23

申请号：US11824214

申请日：2007-06-29

Applicant: Thierry Campiche ,  Martin Miller

Inventor： Thierry Campiche ,  Martin Miller

IPC: H04L7/00

CPC classification number: H04L7/08 ,  G01R13/02 ,  G01R31/31726 ,  G01R31/3183 ,  G01R31/31919 ,  G01R31/31937 ,  G06F3/05 ,  H04L1/08 ,  H04L1/205 ,  H04L7/046

Abstract: A waveform processing system performs operations that may include identifying a location of a specified bit pattern within a coherently sampled repeating pattern input signal. In some examples, multiple periods of a repeating pattern signal are acquired using coherent sampling techniques such as, for example, coherent interleaved sampling (CIS). In such examples, the sampled waveform may be converted to a binary pattern that can be searched to locate a match to a predetermined or user-specified bit pattern. In one illustrative example, the identified location may be used to display the sampled waveform. In another example, the identified location may be used to measure pattern-dependent jitter of the sampled waveform.

Abstract translation: 波形处理系统执行可以包括识别在相干采样的重复图案输入信号内的指定位模式的位置的操作。 在一些示例中，使用诸如相干交织采样（CIS）之类的相干采样技术来获取重复图案信号的多个周期。 在这样的示例中，采样波形可以被转换成可以被搜索以将匹配定位到预定的或用户指定的位模式的二进制模式。 在一个说明性示例中，所识别的位置可以用于显示采样波形。 在另一示例中，所识别的位置可用于测量采样波形的模式相关抖动。

公开(公告)号：US07793022B2

公开(公告)日：2010-09-07

申请号：US12219565

申请日：2008-07-24

Applicant: James Denis Travers ,  Padraig Ryan

Inventor： James Denis Travers ,  Padraig Ryan

IPC: G06F13/00 ,  G06F13/36

CPC classification number: H04L1/243 ,  H04L1/205

Abstract: A digital bit-level repeater for joining two wired-AND buses such as the I2C bus is described. A protocol detector is used for tracking clock and data signals to determine the direction of the transfer. A state machine reads and regenerates the clock lines of both buses and provides the clock-stretching protocol feature on both buses. The repeater is designed to pass data bits from one bus to the other transparently when possible, and to latch and hold each data bit until the receiving bus can be clocked when clock-stretching occurs or when the bus is turned around.

Abstract translation: 描述用于连接诸如I2C总线的两个有线和总线的数字位级中继器。 协议检测器用于跟踪时钟和数据信号以确定传输的方向。 状态机读取并重新生成两条总线的时钟线，并在两条总线上提供时钟延伸协议功能。 中继器被设计为在可能时将数据位从一个总线传输到另一个总线，并且锁存和保持每个数据位，直到当时钟延长发生时或当总线转向时才能对接收总线进行时钟控制。