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    Analog to Digital Converter with Internal Timer
    4.
    发明申请
    Analog to Digital Converter with Internal Timer 有权
    具有内部定时器的模数转换器

    公开(公告)号：US20160336953A1

    公开(公告)日：2016-11-17

    申请号：US14710105

    申请日：2015-05-12

    Applicant: Microchip Technology Incorporated

    Inventor： Vincent Quiquempoix ,  Alexandre Barreto

    IPC: H03M1/34 ,  H03M1/12 ,  H03M1/00

    CPC classification number: H03M1/34 ,  G06F1/3203 ,  G06F1/325 ,  G06F3/05 ,  H03M1/001 ,  H03M1/002 ,  H03M1/12 ,  H03M1/1245

    Abstract: An analog-to-digital converter includes circuitry for receiving an analog input and converting the input to a digital signal; and non-transitory control circuitry configured for: receiving a sampling time; receiving a conversion time; determining a power up time from at least one sleep mode; and causing the digital-to-analog converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time

    Abstract translation: 模数转换器包括用于接收模拟输入并将输入转换成数字信号的电路; 以及非瞬态控制电路，被配置为：接收采样时间; 接收转换时间; 从至少一个睡眠模式确定上电时间; 并且如果上电时间和转换时间的总和小于采样时间，则使数模转换器进入至少一个休眠模式

    Compressed sampling and memory
    5.
    发明授权
    Compressed sampling and memory 有权
    压缩采样和记忆

    公开(公告)号：US09367079B2

    公开(公告)日：2016-06-14

    申请号：US13837676

    申请日：2013-03-15

    Applicant: West Virginia University

    Inventor： Brandon Michael Kelly ,  Brandon David Rumberg ,  David W. Graham

    IPC: G06F1/04 ,  G06F1/14 ,  G06F1/08 ,  G06F3/05 ,  G06F13/24 ,  G06F9/44 ,  H04L12/24 ,  G06F1/32 ,  H04W52/02

    CPC classification number: G06F1/3293 ,  G06F1/08 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/3275 ,  G06F3/05 ,  G06F9/4418 ,  G06F13/24 ,  H04L41/0816 ,  H04W52/02 ,  Y02D10/14 ,  Y02D70/00

    Abstract: Aspects of a low power memory buffer are described. In one embodiment, a sampling rate of a signal is adjusted to identify extrema of a signal. An extrema pulse is generated and, in response to the extrema pulse, a time segment and potential value of the signal are stored in a memory. In other aspects, rising and falling slopes of the signal are tracked to identify a local maximum and a local minimum of the signal. In this scenario, an extrema pulse is generated for each of the local maximum and minimum, and time segment and potential values are stored for the local maximum and minimum. Generally, the storage of analog values of the signal at an adjusted sampling rate is achieved with low power, and the signal may be reconstructed at a later time.

    Abstract translation: 描述低功率存储器缓冲器的方面。 在一个实施例中，调整信号的采样率以识别信号的极值。 产生极值脉冲，并且响应于极值脉冲，信号的时间段和电位值被存储在存储器中。 在其他方面，跟踪信号的上升和下降斜率以识别信号的局部最大值和局部最小值。 在这种情况下，为每个局部最大和最小值生成极值脉冲，并且为局部最大值和最小值存储时间段和电位值。 通常，以低功率实现以调整的采样率存储信号的模拟值，并且可以在稍后的时间重建信号。

    Touch sensing system and method of controlling power consumption thereof, and display device using the same
    6.
    发明授权
    Touch sensing system and method of controlling power consumption thereof, and display device using the same 有权
    触控感应系统及其功耗控制方法及使用其的显示装置

    公开(公告)号：US09329739B2

    公开(公告)日：2016-05-03

    申请号：US14075016

    申请日：2013-11-08

    Applicant: LG DISPLAY CO., LTD.

    Inventor： Kyungjin Jang

    IPC: G06F3/045 ,  G06F3/044 ,  G06F1/32 ,  G06F3/041

    CPC classification number: G06F1/3262 ,  G06F3/0416 ,  G06F3/044 ,  G06F3/05 ,  Y02D50/20

    Abstract: A touch sensing system and a method of controlling power consumption thereof, and a display device using the same are disclosed. The touch sensing system includes a plurality of sensing units, which sample a voltage received from a touch screen and accumulate the sampled voltage, and a plurality of analog-to-digital converters converting an output of the sensing units into digital data. The sensing units and the analog-to-digital converters are divided into a plurality of groups in an idle state. Each of the plurality of groups includes at least two sensing units and one analog-to-digital converter. At least one sensing unit included in at least one group is powered down in the idle state. An analog-to-digital converter is powered on during the group it belongs to is powered on.

    Abstract translation: 公开了一种触摸感测系统及其功率消耗的方法，以及使用该感测系统的显示装置。 触摸感测系统包括多个感测单元，其对从触摸屏接收的电压进行采样并累积采样电压;以及多个模数转换器，将感测单元的输出转换为数字数据。 感测单元和模拟 - 数字转换器在空闲状态下分为多个组。 多个组中的每个组包括至少两个感测单元和一个模拟 - 数字转换器。 包括在至少一个组中的至少一个感测单元在空闲状态下断电。 在其所属的组通电时，模数转换器通电。

    UNIVERSAL PERFORMANCE MONITOR FOR POWER GENERATORS
    7.
    发明申请
    UNIVERSAL PERFORMANCE MONITOR FOR POWER GENERATORS 审中-公开
    发电机通用性能监视器

    公开(公告)号：US20150378420A1

    公开(公告)日：2015-12-31

    申请号：US14605629

    申请日：2015-01-26

    Applicant: VERSIFY SOLUTIONS, INC.

    Inventor： David IPPOLITO ,  David KUCHARCZUK

    IPC: G06F1/32 ,  G06F13/14

    CPC classification number: G06F1/3209 ,  G06F3/05 ,  G06F13/14 ,  H02J13/001 ,  Y04S10/40

    Abstract: The invention broadly encompasses a system including a communications network, a plurality of remotely located data sources to provide power data, the power data including quantitative and qualitative data of one or more power generation units, and a performance monitor in communication with the plurality of remotely located data sources through the communications network, the performance monitor including a communications unit to extract the power data from the plurality of remotely located data sources, a data conversion unit to transform the power data into a common data format, a data store to store the transformed power data, and a user interface unit to display the transformed power data on one or more client devices through the communications network.

    Abstract translation: 本发明广泛地涵盖包括通信网络，多个远程定位的数据源以提供电力数据的系统，包括一个或多个发电单元的定量和定性数据的电力数据，以及与多个远程通信的性能监视器 通过通信网络定位的数据源，性能监视器包括从多个远程位置的数据源提取电力数据的通信单元，将功率数据变换成公共数据格式的数据转换单元，存储数据源 变换的电力数据和用户接口单元，以通过通信网络在一个或多个客户端设备上显示经变换的电力数据。

    Circuit arrangement and method for operating a circuit arrangement
    8.
    发明授权
    Circuit arrangement and method for operating a circuit arrangement 有权
    用于操作电路装置的电路布置和方法

    公开(公告)号：US09147448B2

    公开(公告)日：2015-09-29

    申请号：US13834422

    申请日：2013-03-15

    Applicant: Infineon Technologies AG

    Inventor： Tommaso Bacigalupo ,  Marcus Nuebling

    IPC: G11C7/00 ,  G11C7/12 ,  G06F3/05 ,  G11C27/02 ,  G11C11/412

    CPC classification number: G11C7/12 ,  G06F3/05 ,  G11C11/412 ,  G11C27/02

    Abstract: A circuit arrangement is provided, including a storage circuit and an output circuit. The storage circuit is configured to provide a first output signal and a second output signal. The output circuit is configured to receive the first output signal and the second output signal and configured to provide an output signal having one of a first signal level and a second signal level, and to only switch from the first signal level to the second signal level if the difference between the first output signal and the second output signal exceeds a threshold. The circuit arrangement is configured to hold the first output signal and the second output signal independent of a difference between the first output signal and the second output signal after the switching has been carried out.

    Abstract translation: 提供了一种电路装置，包括存储电路和输出电路。 存储电路被配置为提供第一输出信号和第二输出信号。 输出电路被配置为接收第一输出信号和第二输出信号，并且被配置为提供具有第一信号电平和第二信号电平之一的输出信号，并且仅从第一信号电平切换到第二信号电平 如果第一输出信号和第二输出信号之间的差超过阈值。 电路装置被配置为在执行切换之后，保持与第一输出信号和第二输出信号之间的差无关的第一输出信号和第二输出信号。

    Synchronizing data transfer from a core to a physical interface
    9.
    发明授权
    Synchronizing data transfer from a core to a physical interface 有权
    同步从核心到物理接口的数据传输

    公开(公告)号：US09037893B2

    公开(公告)日：2015-05-19

    申请号：US13852625

    申请日：2013-03-28

    Applicant: ANALOG DEVICES, INC.

    Inventor： Brian Holford ,  Matthew D. McShea

    IPC: G06F1/00 ,  G06F1/04 ,  G06F1/24 ,  G06F5/06 ,  G06F13/42 ,  H04B1/00 ,  H04J3/06

    CPC classification number: G06F1/04 ,  G06F1/24 ,  G06F3/05 ,  G06F13/4243 ,  H04B1/00 ,  H04J3/0685

    Abstract: In one example implementation, the present disclosure provides a system that includes circuitry and one or more electronic components for synchronizing data transfer from a core to a physical interface. One example can involve an apparatus for interfacing a digital core with at least one physical interface that includes a macro configured on the digital core, the macro having at least one data output, a first data input, a reset input and a sync reset output, the macro to be clocked by a first clock having a first clock rate. The first clock can be configured to clock in data from the digital core on the first data input; clock in a reset signal from the digital core on the reset input, wherein a synchronized reset signal is output on the sync reset output. The apparatus can also include physical interface circuitry and a reset sampling input.

    Abstract translation: 在一个示例实现中，本公开提供了一种系统，其包括用于同步从核到物理接口的数据传输的电路和一个或多个电子组件。 一个示例可以涉及用于将数字核与至少一个物理接口进行接口的装置，所述物理接口包括配置在数字内核上的宏，所述宏具有至少一个数据输出，第一数据输入，复位输入和同步复位输出， 由具有第一时钟速率的第一时钟计时的宏。 第一个时钟可以配置为在第一个数据输入端从数字核心的数据进行时钟; 来自复位输入上的数字内核的复位信号中的时钟，其中在同步复位输出上输出同步的复位信号。 该装置还可以包括物理接口电路和复位采样输入。

    Peripheral trigger generator
    10.
    发明授权
    Peripheral trigger generator 有权
    外设触发发生器

    公开(公告)号：US08856406B2

    公开(公告)日：2014-10-07

    申请号：US13613784

    申请日：2012-09-13

    Applicant: Bryan Kris ,  Michael Catherwood

    Inventor： Bryan Kris ,  Michael Catherwood

    IPC: G06F13/12 ,  G06F13/00

    CPC classification number: G06F3/05 ,  G06F1/04 ,  G06F15/7814

    Abstract: A microcontroller includes a central processing unit (CPU); a plurality of peripheral units; and a peripheral trigger generator comprising a user programmable state machine, wherein the peripheral trigger generator is configured to receive a plurality of input signals and is programmable to automate timing functions depending on at least one of said input signals and generate at least one output signal.

    Abstract translation: 微控制器包括中央处理单元（CPU）; 多个外围单元; 以及外围触发发生器，其包括用户可编程状态机，其中所述外围触发发生器被配置为接收多个输入信号，并且可编程以根据所述输入信号中的至少一个自动化定时功能并且生成至少一个输出信号。

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