公开(公告)号：US08563872B2

公开(公告)日：2013-10-22

申请号：US13145271

申请日：2011-02-22

Applicant: Shogo Hirai ,  Hiroyuki Ishitomi ,  Tsuyoshi Himori ,  Satoru Tomekawa ,  Yutaka Nakayama

Inventor： Shogo Hirai ,  Hiroyuki Ishitomi ,  Tsuyoshi Himori ,  Satoru Tomekawa ,  Yutaka Nakayama

IPC: H05K1/11 ,  H05K1/09 ,  H01K3/10

CPC classification number: H05K3/4069 ,  H05K3/4652 ,  H05K2201/0272 ,  H05K2201/0355 ,  H05K2203/0425

Abstract: A wiring board includes a plurality of wirings laid via an insulating resin layer, and a via-hole conductor provided for electrically connecting the wirings. The via-hole conductor includes metal and resin portions. The metal portion includes a region made of copper particles, a first metal region mainly composed of tin, a tin-copper alloy, or a tin-copper intermetallic compound, and a second metal region mainly composed of bismuth, and has Cu/Sn of from 1.59 to 21.43. The copper particles are in contact with one another, thereby electrically connecting the wirings, and at least part of the first metal region covers around and extends over the portions where the copper particles are in plane contact with one another.

Abstract translation: 布线板包括通过绝缘树脂层铺设的多条布线，以及用于电连接布线的通孔导体。 通孔导体包括金属和树脂部分。 金属部分包括由铜颗粒制成的区域，主要由锡，锡 - 铜合金或锡 - 铜金属间化合物构成的第一金属区域和主要由铋组成的第二金属区域，并且具有Cu / Sn 从1.59到21.43。 铜颗粒彼此接触，从而电连接布线，并且第一金属区域的至少一部分围绕并延伸到铜颗粒彼此平面接触的部分上。

公开(公告)号：US20130270218A1

公开(公告)日：2013-10-17

申请号：US13912406

申请日：2013-06-07

Applicant: JX Nippon Mining & Metals Corporation

Inventor： Keisuke Yamanishi ,  Kengo Kaminaga ,  Ryo Fukuchi

IPC: H05K1/09 ,  H05K3/00

CPC classification number: H05K1/09 ,  B32B15/018 ,  C23C26/00 ,  C23C28/021 ,  C23C28/023 ,  C23C28/025 ,  C23C30/00 ,  C23F1/18 ,  H05K3/0073 ,  H05K3/06 ,  H05K2201/0338 ,  H05K2201/0355 ,  Y10T428/12438

Abstract: A rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, characterized in comprising a layer of metal of one or more types among a platinum group, gold and silver with an etching rate that is lower than the copper formed on an etching surface side of the rolled copper foil or the electrolytic copper foil, or alternatively comprising a layer of an alloy having the above-described metal as its main component. The following can be achieved upon forming a circuit by etching a copper foil of a copper clad laminate: sagging caused by the etching is prevented; a uniform circuit of the intended circuit width is formed; the time required to form a circuit by etching is reduced; etching properties in pattern etching are improved; and the occurrence of short circuits and defects in the circuit width are prevented.

Abstract translation: 一种用于通过蚀刻形成电路的电子电路用的卷绕铜箔或电解铜箔，其特征在于，在铂族金，金和银中含有一种或多种类型的金属，其蚀刻速率低于 形成在轧制铜箔或电解铜箔的蚀刻表面侧上的铜，或者可选地包括具有上述金属作为其主要成分的合金层。 通过蚀刻覆铜层压板的铜箔形成电路可以实现以下目的：防止由蚀刻引起的下垂; 形成预期电路宽度的均匀电路; 减少了通过蚀刻形成电路所需的时间; 图案蚀刻中的蚀刻性能得到改善; 并且防止电路宽度的短路和缺陷的发生。

公开(公告)号：US08552305B2

公开(公告)日：2013-10-08

申请号：US12491043

申请日：2009-06-24

Applicant: Jin Seon Park ,  Sung Yi ,  Jung Won Lee

Inventor： Jin Seon Park ,  Sung Yi ,  Jung Won Lee

IPC: H05K1/16

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49894 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/3511 ,  H05K3/321 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/10674 ,  H05K2203/063 ,  H05K2203/1469 ,  H01L2924/00

Abstract: Disclosed herein is an electronic component-embedded printed circuit board including: a base plate including an insulating resin layer and circuit layers; and an electronic component embedded in the insulating resin layer, wherein the insulating resin layer has a thickness 1.3˜3 times greater than that of the electronic component. The electronic component-embedded printed circuit board has an optimum thickness ratio of its constituents in order to minimize the warpage thereof at the time of manufacturing the same.

Abstract translation: 这里公开了一种电子部件嵌入式印刷电路板，包括：基板，包括绝缘树脂层和电路层; 以及埋设在所述绝缘树脂层中的电子部件，所述绝缘树脂层的厚度为所述电子部件的厚度的1.3〜3倍。 电子元件嵌入式印刷电路板具有其成分的最佳厚度比，以便使其制造时的翘曲最小化。

公开(公告)号：US20130256006A1

公开(公告)日：2013-10-03

申请号：US13884650

申请日：2011-11-08

Applicant: Kazuhiko Sakaguchi ,  Hajime Inazumi

Inventor： Kazuhiko Sakaguchi ,  Hajime Inazumi

IPC: H05K3/06 ,  H05K1/09

CPC classification number: H05K3/06 ,  C23F1/02 ,  C23F1/14 ,  C23F1/16 ,  C23F1/44 ,  H05K1/0393 ,  H05K1/09 ,  H05K3/388 ,  H05K2201/0154 ,  H05K2201/0355 ,  Y10T29/49128

Abstract: A method for forming a circuit on a flexible laminate substrate, wherein when a circuit is formed using an adhesive-free flexible laminate having a polyimide film that serves as a flexible laminate substrate at least one surface of which is plasma-treated, a tie-coat layer A formed on the polyimide film, a metal conductor layer B formed on the tie-coat layer, and a nickel-copper alloy layer as an alloy layer C on the metal conductor layer, a photoresist is applied on the alloy layer C formed on the metal conductor layer, the photoresist is exposed and developed, the sputter layer C, the metal conductor layer B, and the alloy layer C are removed by etching using the same etching solution so as to retain a circuit portion, and the photoresist of the circuit portion is further removed so as to form the circuit.

Abstract translation: 一种在柔性层压基板上形成电路的方法，其中当使用不含粘合剂的柔性层压体形成电路时，该层压板具有聚酰亚胺膜，该聚酰亚胺膜用作至少一个表面被等离子体处理的柔性层压基板， 形成在聚酰亚胺膜上的涂层A，在接合涂层上形成的金属导体层B和在金属导体层上作为合金层C的镍 - 铜合金层，在形成的合金层C上施加光致抗蚀剂 在金属导体层上，曝光和显影光致抗蚀剂，通过使用相同的蚀刻溶液进行蚀刻来去除溅射层C，金属导体层B和合金层C，以便保持电路部分，并且光致抗蚀剂 电路部分被进一步去除以形成电路。

公开(公告)号：US20130216855A1

公开(公告)日：2013-08-22

申请号：US13823349

申请日：2012-08-30

Applicant: Tomota Nagaura ,  Kazuhiko Sakaguchi

Inventor： Tomota Nagaura ,  Kazuhiko Sakaguchi

IPC: H05K1/09

CPC classification number: H05K1/09 ,  B32B15/01 ,  C23C18/165 ,  C23C18/31 ,  C23C28/023 ,  C25D1/04 ,  C25D3/04 ,  C25D3/12 ,  C25D3/14 ,  C25D3/16 ,  C25D3/38 ,  C25D3/562 ,  C25D3/565 ,  C25D3/58 ,  C25D5/14 ,  C25D7/0614 ,  C25D9/08 ,  C25D11/38 ,  H05K3/025 ,  H05K2201/0317 ,  H05K2201/032 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2203/0307 ,  Y10T428/12438 ,  Y10T428/12493 ,  Y10T428/12514 ,  Y10T428/12611 ,  Y10T428/12667 ,  Y10T428/12861 ,  Y10T428/12882 ,  Y10T428/1291 ,  Y10T428/12931 ,  Y10T428/12944 ,  Y10T428/12958 ,  Y10T428/24917

Abstract: The present invention provides a carrier-attached copper foil, wherein an ultrathin copper foil is not peeled from the carrier prior to the lamination to an insulating substrate, but can be peeled from the carrier after the lamination to the insulating substrate. A carrier-attached copper foil comprising a copper foil carrier, an intermediate layer laminated on the copper foil carrier, and an ultrathin copper layer laminated on the intermediate layer, wherein the intermediate foil is configured with a Ni layer in contact with an interface of the copper foil carrier and a Cr layer in contact with an interface of the ultrathin copper layer, said Ni layer containing 1,000-40,000 μg/dm2 of Ni and said Cr layer containing 10-100 μg/dm2 of Cr is provided.

Abstract translation: 本发明提供一种载体附着铜箔，其中在层压到绝缘基板之前，超薄铜箔不从载体剥离，而是可以在与绝缘基板层合之后从载体上剥离。 一种载体附着铜箔，包括铜箔载体，层压在所述铜箔载体上的中间层和层压在所述中间层上的超薄铜层，其中所述中间箔配置有与所述中间层的界面接触的Ni层 铜箔载体和与超薄铜层的界面接触的Cr层，所述Ni层含有1,000-40,000mug / dm 2的Ni，所述Cr层含有10-100mug / dm 2的Cr。

公开(公告)号：US08512873B2

公开(公告)日：2013-08-20

申请号：US13055353

申请日：2009-07-22

Applicant: Satoshi Fujisawa ,  Yuji Suzuki ,  Takeo Uno

Inventor： Satoshi Fujisawa ,  Yuji Suzuki ,  Takeo Uno

IPC: B32B15/20

CPC classification number: H05K3/384 ,  B32B15/01 ,  B32B15/08 ,  B32B15/20 ,  B32B27/281 ,  B32B2255/06 ,  B32B2255/205 ,  B32B2307/20 ,  B32B2307/306 ,  B32B2307/50 ,  B32B2307/538 ,  B32B2307/714 ,  B32B2457/08 ,  C22C19/03 ,  C25D3/562 ,  C25D7/0614 ,  H05K1/0346 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2203/0723 ,  Y10T428/12438 ,  Y10T428/12472 ,  Y10T428/12569 ,  Y10T428/12882 ,  Y10T428/1291 ,  Y10T428/12944 ,  Y10T428/12993

Abstract: To provide a surface treated copper foil satisfying all of the bonding strength to polyimide film, chemical resistance, and etching property, and to provide a CCL using the surface treated copper foil, a surface treated copper foil is formed being comprising an untreated copper foil on at least one surface of which Ni—Zn alloy is deposited, wherein Zn content (wt %)=Zn deposition amount/(Ni deposition amount+Zn deposition amount)×100 is 6% or more and 15% or less, and Zn deposition amount is 0.08 mg/dm2 or more, or, a CCL is formed being comprising a surface treated copper foil and a polyimide film laminated on the surface treated copper foil, wherein the surface treated copper foil comprises an untreated copper foil on at least one surface of which Ni—Zn alloy is deposited, Zn content (wt %)=Zn deposition amount/(Ni deposition amount+Zn deposition amount)×100 is 6% or more and 15% or less, and Zn deposition amount is 0.08 mg/dm2 or more.

Abstract translation: 为了提供满足与聚酰亚胺膜的全部接合强度的表面处理铜箔，耐化学性和蚀刻性能，并且使用表面处理铜箔提供CCL，形成表面处理铜箔，其包括未处理的铜箔 其中Zn含量（wt％）= Zn沉积量/（Ni沉积量+ Zn沉积量）×100为6％以上且15％以下，Zn沉积物的至少一个表面为Ni-Zn合金，Zn沉积量 量为0.08mg / dm 2以上，或者由表面处理铜箔和层叠在表面处理铜箔上的聚酰亚胺膜形成CCL，其中表面处理铜箔在至少一个表面上包含未处理的铜箔 其中沉积Ni-Zn合金，Zn含量（wt％）= Zn沉积量/（Ni沉积量+ Zn沉积量）×100为6％以上且15％以下，Zn沉积量为0.08mg / dm2以上。

公开(公告)号：US08470680B2

公开(公告)日：2013-06-25

申请号：US12180768

申请日：2008-07-28

Applicant: John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Antony P. Chacko ,  Gregory J. Dunn

Inventor： John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Antony P. Chacko ,  Gregory J. Dunn

IPC: H01G4/005

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G9/042 ,  H01G9/045 ,  H01G9/15 ,  H05K3/429 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09909 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/435

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

公开(公告)号：US08468693B2

公开(公告)日：2013-06-25

申请号：US12868425

申请日：2010-08-25

Applicant: Tomohiko Katoh ,  Kenji Horino ,  Yuko Saya

Inventor： Tomohiko Katoh ,  Kenji Horino ,  Yuko Saya

IPC: H01R43/02

CPC classification number: H01G4/33 ,  H01G4/008 ,  H01L27/016 ,  H05K1/162 ,  H05K3/38 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/2063 ,  H05K2203/1105 ,  Y10T29/49126 ,  Y10T29/49163 ,  Y10T29/49204 ,  Y10T29/49213

Abstract: A dielectric device has a first conductor and a dielectric disposed thereon. An intermediate region is formed between the first conductor and dielectric. In the intermediate region, an additive different from the first conductor and dielectric and the dielectric are mixed with each other. The additive contains at least one element of Si, Al, P, Mg, Mn, Y, V, Mo, Co, Nb, Fe, and Cr.

Abstract translation: 电介质器件具有设置在其上的第一导体和电介质。 在第一导体和电介质之间形成中间区域。 在中间区域中，与第一导体和电介质和电介质不同的添加剂彼此混合。 添加剂含有Si，Al，P，Mg，Mn，Y，V，Mo，Co，Nb，Fe和Cr中的至少一种元素。

公开(公告)号：US08398869B2

公开(公告)日：2013-03-19

申请号：US12277391

申请日：2008-11-25

Applicant: Paul Attridge ,  Foster P. Lamm

Inventor： Paul Attridge ,  Foster P. Lamm

IPC: H01B13/00 ,  C23F1/02

CPC classification number: H05K3/20 ,  H05K1/185 ,  H05K1/187 ,  H05K3/06 ,  H05K2201/0355 ,  H05K2203/0156

Abstract: A method of fabricating a circuit includes bonding an electrically conductive layer to a carrier film using an adhesive selected from acrylic polymer and silicone polymer, removing selected portions of the electrically conductive layer from the carrier film to provide a circuit arrangement, and transferring the circuit arrangement from the carrier film to a substrate.

Abstract translation: 一种制造电路的方法包括使用选自丙烯酸聚合物和硅氧烷聚合物的粘合剂将导电层粘合到载体膜上，从载体膜去除导电层的选定部分以提供电路布置，并将电路装置 从载体膜到基底。

公开(公告)号：US08393076B2

公开(公告)日：2013-03-12

申请号：US12531856

申请日：2008-03-17

Applicant: Philip Gareth Bentley

Inventor： Philip Gareth Bentley

IPC: H05K3/30

CPC classification number: H05K1/188 ,  G06K19/07745 ,  G06K19/07747 ,  G06K19/07749 ,  G06K19/0775 ,  H01L21/56 ,  H01L23/4822 ,  H01L24/12 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81801 ,  H01L2224/83121 ,  H01L2224/83851 ,  H01L2224/90 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/189 ,  H05K3/061 ,  H05K3/202 ,  H05K2201/0355 ,  H05K2201/09118 ,  H05K2201/10674 ,  H05K2203/1469 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A component is electrically connected to an electrical circuit by a method that comprises forming an intermediate product in which the component (3) is disposed on one side of an electrically conducting sheet (1) so that at least one pair of contacts (4) of the component are electrically connected by the sheet and in which a patterned etch resist layer (2) is disposed on the other side of the sheet in registration with the component on said one side of the sheet, and then exposing the other side of the sheet to an etching agent and thereby removing areas of the sheet to leave the electrical circuit and also to remove the electrical interconnection between the contacts.

Abstract translation: 组件通过包括形成中间产品的方法电连接到电路，其中组件（3）设置在导电片（1）的一侧上，使得至少一对触点（4）的 该部件通过片材电连接，并且其中图案化的抗蚀剂层（2）设置在片材的另一侧上，与片材的所述一侧上的部件对准，然后暴露片材的另一侧 到蚀刻剂，从而去除片材的区域以离开电路，并且还去除接触件之间的电互连。