中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

430 records (took 0.016 seconds)

    Arrangement of integrated circuits in a memory module
    71.
    发明申请
    Arrangement of integrated circuits in a memory module 有权
    集成电路在存储器模块中的布置

    公开(公告)号：US20040184300A1

    公开(公告)日：2004-09-23

    申请号：US10765488

    申请日：2004-01-27

    Inventor： Jayesh R. Bhakta ,  Robert S. Pauley JR.

    IPC: G11C005/06

    CPC classification number: H05K1/181 ,  H05K1/0266 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10689 ,  Y02P70/611

    Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

    Abstract translation: 使用标准商业包装的集成电路布置在印刷电路板上，以允许生产1千兆字节和2千兆字节容量的存储器模块。 第一排集成电路定向成与第二排集成电路相反的方向。 第一行的前半部分和第二行的相应一半中的集成电路经由信号迹线连接到第一寄存器。 第一行的后半部分和第二行的相应一半中的集成电路连接到第二寄存器。 每个寄存器处理每个数据字中位的不连续子集。

    Method for the connection and repair of flex and other circuits
    72.
    发明授权
    Method for the connection and repair of flex and other circuits 失效
    柔性和其他电路的连接和修复方法

    公开(公告)号：US06601292B2

    公开(公告)日：2003-08-05

    申请号：US09891697

    申请日：2001-06-26

    Applicant: Delin Li ,  Jay DeAvis Baker ,  Achyuta Achari ,  Brenda Joyce Nation ,  John Trublowski

    Inventor： Delin Li ,  Jay DeAvis Baker ,  Achyuta Achari ,  Brenda Joyce Nation ,  John Trublowski

    IPC: H05K300

    CPC classification number: H05K3/361 ,  H05K1/0293 ,  H05K1/117 ,  H05K1/118 ,  H05K3/0052 ,  H05K3/225 ,  H05K2201/053 ,  H05K2201/09127 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/0979 ,  H05K2203/0228 ,  H05K2203/175 ,  Y10T29/49124 ,  Y10T29/49169 ,  Y10T29/4973 ,  Y10T29/49732

    Abstract: A method for making and repairing connections between first and second circuits, such as flex circuits. An article 10 includes: a flexible dielectric substrate 12 having first and second edges 14/16, and a plurality of conductive circuit traces 18 arranged on or within the substrate, wherein each of the traces extends from proximate the first edge 14 to proximate the second edge 16. Each of the circuit traces 18 includes: a first connection feature 20 disposed proximate the first edge 14; a second connection feature 22 disposed proximate the second edge 16; and at least one third connection feature 24 disposed between the first and second edges 14/16. Each of the first, second, and third connection features 20/22/24 is a plated through hole, a plated blind via, or a mounting pad. This article 10 may be used to connect together the first and second circuits 50/60 using the first and second connection features 20/22, such as by soldering. If either of the two circuits needs to be subsequently detached (e.g., because of a component failure), the article 10 may be cut so as to present a set of third connection features 24 to which a new replacement circuit may be connected.

    Abstract translation: 用于制造和修复第一和第二电路之间的连接的方法，例如柔性电路。 物品10包括：具有第一和第二边缘14/16的柔性电介质基底12和布置在基底上或内部的多个导电电路迹线18，其中每个迹线从靠近第一边缘14延伸到接近第二边缘14 每个电路迹线18包括：靠近第一边缘14设置的第一连接特征20; 设置在第二边缘16附近的第二连接特征22; 以及设置在第一和第二边缘14/16之间的至少一个第三连接特征24。 第一，第二和第三连接特征20/22/24中的每一个是电镀通孔，电镀盲孔或安装垫。 本文10可以用于使用第一和第二连接特征20/22（例如通过焊接）将第一和第二电路50/60连接在一起。 如果两个电路中的任一个需要随后分离（例如，由于部件故障），则可以切割物品10以便呈现一组第三连接特征24，新的替换电路可以连接到该组。

    Electronic printed circuit board having a plurality of identically designed, housing-encapsulated semiconductor memories
    75.
    发明申请
    Electronic printed circuit board having a plurality of identically designed, housing-encapsulated semiconductor memories 有权
    具有多个相同设计的外壳封装的半导体存储器的电子印刷电路板

    公开(公告)号：US20030002262A1

    公开(公告)日：2003-01-02

    申请号：US10187763

    申请日：2002-07-02

    Inventor： Martin Benisek ,  Martin Schober

    IPC: H05K007/00

    CPC classification number: H05K1/181 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/10689 ,  Y02P70/611

    Abstract: An electronic printed circuit board has a memory module and a contact strip for insertion into another electronic unit. The memory module has at least nine identically designed housing-encapsulated integrated semiconductor memories configured on the printed circuit board. The longer dimension of the housing of one of the semiconductor memories, which is connected as an error correction chip, is oriented perpendicular to the contact strip. The longer dimension of the housings of the other semiconductor memories are oriented parallel to the contact strip. The different orientation of the semiconductor memories makes it possible to reduce the height of the printed circuit board while enabling the rectangular housings to keep the same physical form.

    Abstract translation: 电子印刷电路板具有用于插入另一个电子单元的存储器模块和接触条。 存储器模块具有至少九个相同设计的外壳封装集成半导体存储器，其被配置在印刷电路板上。 作为误差校正芯片连接的半导体存储器之一的外壳的较长尺寸垂直于接触片定向。 其他半导体存储器的壳体的较长尺寸定向成平行于接触条。 半导体存储器的不同取向使得可以降低印刷电路板的高度，同时使矩形壳体保持相同的物理形式。

    Mounting structure for module substrates
    76.
    发明申请
    Mounting structure for module substrates 有权
    模块底板的安装结构

    公开(公告)号：US20020131258A1

    公开(公告)日：2002-09-19

    申请号：US09995643

    申请日：2001-11-29

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Keiji Inoue ,  Yasuo Ohashi ,  Toru Yoshikawa

    IPC: H05K001/14

    CPC classification number: H05K1/144 ,  H05K1/0269 ,  H05K1/141 ,  H05K3/303 ,  H05K3/3426 ,  H05K3/368 ,  H05K2201/09409 ,  H05K2201/10386 ,  H05K2203/082 ,  H05K2203/1572 ,  H05K2203/161 ,  H05K2203/168

    Abstract: A plurality of module substrates have circuit boards, respectively. The circuit boards are stacked with a space therebetween, and are connected to first end portions of connecting members. The second end portions of the connecting members are connected to connecting pads disposed on a motherboard. The module substrates are thus stacked and mounted on the motherboard so as to increase the mounting density. By causing the connecting members for the upper circuit board to project further than the connecting members for the lower circuit board, the connecting members for the upper and lower circuit boards are prevented from touching each other.

    Abstract translation: 多个模块基板分别具有电路板。 电路板在它们之间堆叠起来，并连接到连接件的第一端部。 连接构件的第二端部连接到设置在母板上的连接垫。 因此，模块基板堆叠并安装在母板上，以增加安装密度。 通过使上部电路基板的连接部件比下部电路基板的连接部件进一步突出，能够防止上下电路基板的连接部件相互接触。

    Electrical connector assembly with improved contact arrangement
    77.
    发明授权
    Electrical connector assembly with improved contact arrangement 失效
    具有改进的接触布置的电连接器组件

    公开(公告)号：US06419502B1

    公开(公告)日：2002-07-16

    申请号：US09808780

    申请日：2001-03-14

    Applicant: John D. Trammel

    Inventor： John D. Trammel

    IPC: H01R1220

    CPC classification number: H05K1/117 ,  H01R12/721 ,  H01R24/62 ,  H05K2201/09409 ,  H05K2201/10189 ,  H05K2201/10356

    Abstract: An electrical connector assembly (1) for connecting to a cable includes a first connector (10), a second connector (20) mateable with the first connector, and a PCB (30). The first connector comprises a first housing (12) and a plurality of contacts (14) retained in the first housing. The contacts have mating portions (142) arranged in a single row for engaging with a corresponding terminal (24) of the second connector, and soldering portions (144) arranged in upper and lower rows for connecting to circuit traces (32, 36) of the PCB. The soldering portions are arranged in adjacent groups of three having a fine pitch for being soldered to corresponding circuit traces. Rows of second and fourth circuit traces (34, 38) are also formed on the PCB, having a larger spacing than the fine pitch of the soldering portions for facilitating soldering of corresponding conductors of the cable thereto.

    Abstract translation: 用于连接到电缆的电连接器组件（1）包括第一连接器（10），可与第一连接器配合的第二连接器（20）和PCB（30）。 第一连接器包括第一壳体（12）和保持在第一壳体中的多个触点（14）。 触点具有布置成单列的配合部分（142），用于与第二连接器的相应端子（24）接合，以及布置在上部和下部行中的焊接部分（144），用于连接到电路迹线（32,36） PCB。 焊接部分布置成具有细间距的三个相邻组，用于焊接到相应的电路迹线。 第二和第四电路迹线（34,38）的行也形成在PCB上，具有比焊接部分的细间距更大的间隔，以便于将电缆的相应导体焊接到其上。

    Liquid crystal display panels including alignment patterns and related methods
    79.
    发明授权
    Liquid crystal display panels including alignment patterns and related methods 失效
    液晶显示面板包括对准图案和相关方法

    公开(公告)号：US06198519B1

    公开(公告)日：2001-03-06

    申请号：US08808887

    申请日：1997-02-28

    Applicant: Jong-woong Chang

    Inventor： Jong-woong Chang

    IPC: G02F11337

    CPC classification number: G02F1/13452 ,  H05K1/0269 ,  H05K1/117 ,  H05K3/361 ,  H05K2201/09409 ,  H05K2201/09781 ,  H05K2203/166 ,  Y10T29/49126

    Abstract: A liquid crystal display includes a liquid crystal display panel having a face and a data/gate pad on the face of the liquid crystal display panel wherein the data/gate pad includes a metal layer. A dummy pad is also on the face of the liquid crystal display panel wherein the dummy pad includes an alignment pattern therein. In particular, the alignment pattern can be a vernier pattern. Related methods are also discussed.

    Abstract translation: 液晶显示器包括在液晶显示面板的表面上具有面部的液晶显示面板和数据/栅极焊盘，其中数据/栅极焊盘包括金属层。 虚拟垫也在液晶显示面板的表面上，其中虚拟垫包括其中的取向图案。 特别地，对准图案可以是游标图案。 还讨论了相关方法。

Patent Agency Ranking