公开(公告)号：US08120877B2

公开(公告)日：2012-02-21

申请号：US12327720

申请日：2008-12-03

Applicant: Eun Kyu Jang

Inventor： Eun Kyu Jang

IPC: G11B5/48

CPC classification number: H05K1/025 ,  G11B5/4846 ,  H05K1/0253 ,  H05K1/147 ,  H05K2201/0969 ,  H05K2201/10189

Abstract: This application discloses a hard disk drive, a head stack assembly, and a printed circuit board configured to include impedance patches on the flex ground plane, the flex power plane, the printed circuit ground plane and/or the printed circuit power plane over or under a connector site in the disk base that conveys access read and write differential signals for the sliders' access of rotating disk surfaces. These impedance patches minimize impedance discontinuities in the read and/or write differential signals through the connector site, which may improve the ability of the hard disk drive to transmit these signals at higher frequencies.

Abstract translation: 本申请公开了一种硬盘驱动器，磁头堆叠组件和印刷电路板，其被配置为在柔性接地平面，柔性电源平面，印刷电路接地平面和/或印刷电路电源平面上包括阻抗贴片， 磁盘基座中的连接器位置传送访问读取和写入用于滑块访问旋转磁盘表面的差分信号。 这些阻抗补丁最大限度地减少了通过连接器位置读取和/或写入差分信号的阻抗不连续性，这可能会提高硬盘驱动器在较高频率下传输这些信号的能力。

公开(公告)号：US08119921B1

公开(公告)日：2012-02-21

申请号：US12001941

申请日：2007-12-13

Applicant: Joel R. Goergen ,  Greg Hunt ,  Peter Tomaszewski ,  Joseph Pankow ,  Michael Laudon

Inventor： Joel R. Goergen ,  Greg Hunt ,  Peter Tomaszewski ,  Joseph Pankow ,  Michael Laudon

IPC: H05K1/03

CPC classification number: H05K1/111 ,  H05K1/0245 ,  H05K2201/0187 ,  H05K2201/0969 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The characteristic impedance of a surface pad is manipulated by reticulating the pad and filling the spaces with a dielectric material, providing an inductive element in the coupling of the surface pad to an underlying ground pad of a ground plane, or a combination of these approaches. In appropriate embodiments, acceptable signal trace routing paths will exist in an embedded signal layer under the ground plane and crossing under the surface pad. Other embodiments are also described and claimed.

Abstract translation: 表面焊盘的特征阻抗是通过网状网格化和用介电材料填充空间来操作的，在表面焊盘与接地平面的下方接地焊盘的耦合中提供电感元件，或这些方法的组合。 在适当的实施例中，可接受的信号迹线路由路径将存在于地平面下方的嵌入式信号层中，并在表面焊盘下交叉。 还描述和要求保护其他实施例。

公开(公告)号：US08110747B2

公开(公告)日：2012-02-07

申请号：US12430133

申请日：2009-04-27

Applicant: Shou-Kuo Hsu ,  Chia-Nan Pai

Inventor： Shou-Kuo Hsu ,  Chia-Nan Pai

IPC: H05K1/00

CPC classification number: H05K1/0245 ,  H05K1/0253 ,  H05K1/0393 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0969

Abstract: A flexible printed circuit board (FPCB) includes a signal layer, upper and lower ground layers, and two dielectric layers. The signal layer includes a differential pair comprising two transmission lines to transmit a pair of differential signals. The dielectric layers are located on and under the signal layer to sandwich the signal layer. The upper ground layer is attached to the dielectric layer on the signal layer, opposite to the signal layer. The lower ground layer is attached to the dielectric layer under the signal layer, opposite to the signal layer. Each ground layer includes a grounded sheet made of conductive material. Two voids are defined in each ground layer and located at opposite sides of the corresponding grounded sheet. Distances between the middle line of the grounded sheet of each ground layer and middle lines of the two transmission lines are equal.

Abstract translation: 柔性印刷电路板（FPCB）包括信号层，上下接地层和两个电介质层。 信号层包括差分对，该差分对包括用于发送一对差分信号的两条传输线。 电介质层位于信号层之上和之下，以夹住信号层。 上层接地层与信号层的电介质层相连，与信号层相反。 下部接地层附着在与信号层相反的信号层下面的电介质层上。 每个接地层包括由导电材料制成的接地片。 在每个接地层中定义两个空隙，并且位于相应接地片的相对侧。 每个接地层的接地片的中间线与两条传输线的中间线之间的距离相等。

公开(公告)号：US20110315440A1

公开(公告)日：2011-12-29

申请号：US13137632

申请日：2011-08-30

Applicant: Han Kim

Inventor： Han Kim

IPC: H05K1/11

CPC classification number: H01P1/2005 ,  H01Q15/006 ,  H01Q15/008 ,  H05K1/0236 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/0969

Abstract: An electromagnetic bandgap structure and a printed circuit board that have a mushroom type structure. The electromagnetic bandgap structure includes a first metal layer; a first dielectric layer, layer-built on the first metal layer; a mushroom type structure having a metal plate layer-built on the first dielectric layer and a via of which one end is connected to the metal plate; a second dielectric layer, layer-built on the metal plate and the first dielectric layer; and a second metal layer, layer-built on the second dielectric layer, wherein the other end of the via is placed in a hole formed on the first metal layer and is connected to the first metal layer through a metal line.

Abstract translation: 具有蘑菇型结构的电磁带隙结构和印刷电路板。 电磁带隙结构包括第一金属层; 第一电介质层，其被构建在第一金属层上; 具有建立在第一电介质层上的金属板层的蘑菇型结构和其一端连接到金属板的通孔; 第二电介质层，层叠在金属板和第一介电层上; 以及第二金属层，其构造在所述第二电介质层上，其中所述通孔的另一端位于形成在所述第一金属层上的孔中，并且通过金属线连接到所述第一金属层。

公开(公告)号：US20110310568A1

公开(公告)日：2011-12-22

申请号：US13163200

申请日：2011-06-17

Applicant: Tao Hong ,  Markus Thoben

Inventor： Tao Hong ,  Markus Thoben

IPC: H05K1/14 ,  H01L29/86

CPC classification number: H05K1/181 ,  G01R1/203 ,  H01L23/647 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L25/16 ,  H01L25/18 ,  H01L27/0207 ,  H01L28/20 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K3/222 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2203/173 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/83205

Abstract: A circuit arrangement has a populated circuit carrier and includes a flat insulation carrier having a top side and a patterned metallization layer on the top side and a first power semiconductor chip arranged on a first section of the metallization layer. The first power semiconductor chip has a first lower chip load terminal electrically conductively connected to the first section. A shunt resistor is arranged on a second section of the metallization layer. The shunt resistor has a lower main terminal electrically conductively connected to the second section. An electrically conductive connection is provided between the first section and the second section. The electrically conductive connection includes a constriction between the first section and the second section so that a current which flows between the first lower chip load terminal and the lower main terminal during operation of the circuit arrangement must pass through the constriction.

Abstract translation: 电路装置具有填充电路载体，并且包括在顶侧具有顶侧和图案化金属化层的平坦绝缘载体和布置在金属化层的第一部分上的第一功率半导体芯片。 第一功率半导体芯片具有导电连接到第一部分的第一下部芯片负载端子。 分流电阻器布置在金属化层的第二部分上。 分流电阻器具有导电连接到第二部分的下主端子。 在第一部分和第二部分之间提供导电连接。 导电连接包括第一部分和第二部分之间的收缩部分，使得在电路装置的操作期间在第一下部芯片负载端子和下部主端子之间流动的电流必须通过收缩部。

公开(公告)号：US08017874B2

公开(公告)日：2011-09-13

申请号：US12388953

申请日：2009-02-19

Applicant: Mitsuru Honjo ,  Katsutoshi Kamei

Inventor： Mitsuru Honjo ,  Katsutoshi Kamei

IPC: H05K1/00

CPC classification number: H05K1/0248 ,  G11B5/484 ,  G11B5/4853 ,  G11B5/486 ,  H05K1/0219 ,  H05K1/0224 ,  H05K1/0245 ,  H05K1/0253 ,  H05K1/056 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0969

Abstract: A first insulating layer is formed on a suspension body, and a write wiring trace is formed on the first insulating layer. A second insulating layer is formed on the first insulating layer so as to cover the wiring trace. A write wiring trace is formed, above the write wiring trace, on the second insulating layer. A ground trace is formed on one side of the write wiring trace at a distance on the second insulating layer. A third insulating layer is formed on the second insulating layer so as to cover the wiring trace and the ground trace. An opening is formed in a region, below the write wiring trace, of the suspension body.

Abstract translation: 在悬架体上形成第一绝缘层，在第一绝缘层上形成写入布线。 在第一绝缘层上形成第二绝缘层以覆盖布线迹线。 在第二绝缘层上形成写入布线迹线上方的写入布线。 在第二绝缘层上一定距离地在写入布线迹线的一侧上形成接地迹线。 在第二绝缘层上形成第三绝缘层，以覆盖布线迹线和接地迹线。 在悬挂体的写入配线轨迹的下方的区域形成有开口部。

公开(公告)号：US08017871B2

公开(公告)日：2011-09-13

申请号：US12457874

申请日：2009-06-24

Applicant: Toshiki Naito ,  Tetsuya Ohsawa ,  Kouji Kataoka

Inventor： Toshiki Naito ,  Tetsuya Ohsawa ,  Kouji Kataoka

IPC: H05K1/00

CPC classification number: H05K1/0269 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/225 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2201/0969 ,  H05K2201/09781 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/53022 ,  Y10T29/53026 ,  Y10T29/5303 ,  Y10T29/53035 ,  Y10T29/53039 ,  Y10T29/53043

Abstract: A wired circuit board assembly sheet has a plurality of wired circuit boards, distinguishing marks for distinguishing defectiveness of the wired circuit boards, and a supporting sheet for supporting the plurality of wired circuit boards and the distinguishing marks. Each of the distinguishing marks has an indication portion for indicating a specified one of the wired circuit boards.

公开(公告)号：US20110217853A1

公开(公告)日：2011-09-08

申请号：US12879951

申请日：2010-09-10

Applicant: Pascal Cornic ,  Jean-Philippe Coupez ,  Jérémie Hemery ,  Julien Boucher

Inventor： Pascal Cornic ,  Jean-Philippe Coupez ,  Jérémie Hemery ,  Julien Boucher

IPC: H01R12/00

CPC classification number: H05K1/0243 ,  H01P5/085 ,  H05K1/0219 ,  H05K1/025 ,  H05K1/0253 ,  H05K2201/09618 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/09809 ,  H05K2201/10189

Abstract: A connection device for high frequency signals includes a printed circuit on one external face of which is printed a transmission line and a coaxial connector surface mounted on the printed circuit on the external face. The invention is of particular use for the transmission of radiofrequency signals in the X band, in particular for frequencies from 9 to 10 GHz. The transmission line is connected to the connector by means of a bump contact belonging to the transmission line to which is attached a central core of the connector. The printed circuit comprises at least one internal ground plane parallel to the external face and contributing to the matching of the transmission line. The invention aims to improve the transparency of the transition between the connector and the transmission line. According to the invention, the internal ground plane is perforated by means of a resist facing the bump contact.

Abstract translation: 用于高频信号的连接装置包括一个外表面上印有传输线的印刷电路和安装在外表面上的印刷电路上的同轴连接器表面。 本发明特别用于X频段中的射频信号的传输，特别是用于9至10GHz的频率。 传输线通过属于连接有连接器的中心芯的传输线的凸块接触件连接到连接器。 印刷电路包括平行于外表面的至少一个内部接地平面并有助于传输线的匹配。 本发明旨在提高连接器与传输线之间的过渡的透明度。 根据本发明，通过面向凸块接触的抗蚀剂对内部接地平面进行穿孔。

公开(公告)号：US20110203935A1

公开(公告)日：2011-08-25

申请号：US13098764

申请日：2011-05-02

Applicant: Jeong Hyun PARK

Inventor： Jeong Hyun PARK

IPC: G01R31/28 ,  C25D7/00

CPC classification number: H05K3/4679 ,  H01L22/34 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K3/4644 ,  H05K2201/0969 ,  H05K2201/09909 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00

Abstract: An apparatus for detecting pattern alignment error includes a first conductive pattern disposed over a first insulation member with a power source applied of the first conductive pattern; a second insulation member for covering the first conductive pattern; a second conductive pattern disposed on the second insulation member; a conductive via connected to the second conductive pattern and passing through the second insulation member; and an insulation pattern disposed in the first conductive pattern for detecting an alignment error in response to a position of the conductive via. The apparatus for detecting pattern alignment error can detect the alignment of lower wiring in a device with multi-layer wiring

Abstract translation: 一种用于检测图案对准误差的装置包括：设置在第一绝缘构件上的第一导电图案，其中施加有第一导电图案的电源; 用于覆盖第一导电图案的第二绝缘构件; 布置在所述第二绝缘构件上的第二导电图案; 连接到第二导电图案并穿过第二绝缘构件的导电通孔; 以及设置在第一导电图案中的绝缘图案，用于响应于导电通孔的位置检测对准误差。 用于检测图案对准误差的装置可以检测具有多层布线的装置中的下布线的对准

公开(公告)号：US20110100686A1

公开(公告)日：2011-05-05

申请号：US12656643

申请日：2010-02-05

Applicant: Watanabe Ryoichi ,  Se Won Park

Inventor： Watanabe Ryoichi ,  Se Won Park

IPC: H05K1/09 ,  H01K3/10

CPC classification number: H05K3/4038 ,  H05K1/116 ,  H05K3/421 ,  H05K2201/0969

Abstract: The present invention provides a printed circuit board including: a circuit pattern formed on a first insulating layer; a via pad disposed on the first insulating layer by being spaced apart from the circuit pattern, formed on a lower surface, where a via hole is formed, to have a cross section larger than that of the via hole, and having concavo-convex patterns; a second insulating layer formed on the via pad where the via hole is not formed and on the circuit pattern; and a copper foil layer formed on the second insulating layer and the via hole, and a method of manufacturing the same.

Abstract translation: 本发明提供一种印刷电路板，包括：形成在第一绝缘层上的电路图案; 形成在形成有通孔的下表面上的与电路图案间隔开的第一绝缘层上的通孔焊盘的横截面积大于通路孔的横截面，并具有凹凸图案 ; 形成在通孔焊盘上的第二绝缘层，其中没有形成通孔并且在电路图案上; 以及形成在第二绝缘层和通孔上的铜箔层及其制造方法。