公开(公告)号：US4914814A

公开(公告)日：1990-04-10

申请号：US347305

申请日：1989-05-04

Applicant: John R. Behun ,  William R. Miller ,  Bert H. Newman ,  Edward L. Yankowski

Inventor： John R. Behun ,  William R. Miller ,  Bert H. Newman ,  Edward L. Yankowski

IPC: H01R12/04 ,  H01L23/50 ,  H05K3/34

CPC classification number: H05K3/3436 ,  H05K3/3478 ,  H01L2224/16225 ,  H05K2201/0379 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/043 ,  H05K2203/0557 ,  Y02P70/613 ,  Y10T29/49149

Abstract: A low cost process for fabricating solder column interconnectons for an electronic package is described. The process includes the step of filling an array of pin holes in a pin mold with a lead/tin solder, which array of pin holes is in substantial registration with the array of conductive pads on one side of a chip carrier; heating the lead/tin solder in the pin mold such that the solder becomes molten and coalesces with the array of conductive pads of the chip carrier, thereby forming an array of miniature pins bonded to the array of conductive pads of the chip carrier; joining circuit components to the other side of the chip carrier; and reflowing an eutectic lead/tin solder paste screened to the corresponding array of conductive pads of a circuit board to bond the free ends of the array of miniature pins of the carrier to the corresponding array of conductive pads, thereby forming the solder column connnections between the chip carrier and the circuit board. The process is suitable for mass production of reliable, high-density electrical interconnections between a chip carrier and a supporting circuit board.

公开(公告)号：US4268585A

公开(公告)日：1981-05-19

申请号：US911307

申请日：1978-06-01

Applicant: Rolf Daur ,  Herbert Hoffmann ,  Gunter Schmid

Inventor： Rolf Daur ,  Herbert Hoffmann ,  Gunter Schmid

IPC: B23K1/19 ,  B23K35/00 ,  H01R43/02 ,  H05K3/34 ,  H05K1/09 ,  H05K3/12 ,  H05K3/28

CPC classification number: H05K3/3463 ,  B23K1/19 ,  B23K35/007 ,  H01R43/02 ,  H05K2201/10992 ,  Y10S428/901 ,  Y10T428/12535 ,  Y10T428/12542 ,  Y10T428/12556 ,  Y10T428/12715 ,  Y10T428/12889 ,  Y10T428/24917

Abstract: A method of applying solder to gold by applying a gold-tin intermediate layer to the gold and applying the solder over at least a portion of the intermediate layer. The method can be employed to produce a printed circuit unit composed of a printed circuit board, at least one gold member mounted on the board, a gold-tin intermediate layer bonded to at least a portion of the gold member, and solder bonded onto the intermediate layer.

Abstract translation: 通过将金锡中间层施加到金上并将焊料涂覆在中间层的至少一部分上来将焊料施加到金的方法。 该方法可以用于制造印刷电路单元，该印刷电路单元由印刷电路板，安装在板上的至少一个金构件，与金构件的至少一部分接合的金锡中间层和焊接到 中间层。

公开(公告)号：US20170374743A1

公开(公告)日：2017-12-28

申请号：US15699570

申请日：2017-09-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Arata KISHI ,  Hironori MUNAKATA ,  Koji MOTOMURA ,  Hiroki MARUO

IPC: H05K1/18 ,  H01L23/00 ,  H05K3/34

CPC classification number: H05K1/181 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/10156 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32052 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/81052 ,  H01L2224/81191 ,  H01L2224/8159 ,  H01L2224/81609 ,  H01L2224/81611 ,  H01L2224/81613 ,  H01L2224/81639 ,  H01L2224/81647 ,  H01L2224/81815 ,  H01L2224/81935 ,  H01L2224/81951 ,  H01L2224/81986 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/384 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K2201/2009 ,  H05K2201/2036 ,  H05K2201/2045 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A mounting structure includes a bonding material (106) that bonds second electrodes (104) of a circuit board (105) and bumps (103) of a semiconductor package (101), the bonding material (106) being surrounded by a first reinforcing resin (107). Moreover, a portion between the outer periphery of the semiconductor package (101) and the circuit board (105) is covered with a second reinforcing resin (108). Even if the bonding material (106) is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained.

公开(公告)号：US20160302306A1

公开(公告)日：2016-10-13

申请号：US14958031

申请日：2015-12-03

Applicant: VIA Alliance Semiconductor Co., Ltd.

Inventor： Nai-Shung CHANG ,  Wen-Yuan CHANG ,  Kuo-Ying TSAI

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/111 ,  H01L25/00 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0204 ,  H05K1/141 ,  H05K1/144 ,  H05K3/3436 ,  H05K2201/09381 ,  H05K2201/10992 ,  Y02P70/611 ,  H01L2924/00012

Abstract: An electronic package assembly is provided. The electronic package assembly includes a package substrate having a first surface and a second surface opposite thereto. A plurality of conductive pads is disposed on the first surface. A chip is mounted onto the first surface of the package substrate. A circuit board is mounted onto the second surface of the package substrate, and includes an electrical connector. A plurality of electrical contact components is electrically connected to the electrical connector and is in contact with the plurality of conductive pads.

Abstract translation: 提供电子封装组件。 电子封装组件包括具有第一表面和与其相对的第二表面的封装衬底。 多个导电垫设置在第一表面上。 芯片安装在封装基板的第一表面上。 电路板安装在封装基板的第二表面上，并且包括电连接器。 多个电接触部件电连接到电连接器并且与多个导电焊盘接触。

公开(公告)号：US20150314396A1

公开(公告)日：2015-11-05

申请号：US14648031

申请日：2013-11-18

Applicant: SENJU METAL INDUSTRY CO., LTD.

Inventor： Koji WATANABE ,  Minoru TOYODA ,  Satoshi TOMITA ,  Tsutomu SUGINO ,  Daichi KIKUCHI ,  Hiroki OSHIMA

IPC: B23K35/02 ,  B23K35/28 ,  B23K1/00 ,  B23K1/19 ,  B32B15/01 ,  C22C13/00 ,  C22C13/02 ,  C22C12/00 ,  C22C11/06 ,  B23K35/26 ,  H05K3/34

CPC classification number: B23K35/0238 ,  B23K1/0016 ,  B23K1/19 ,  B23K35/0222 ,  B23K35/0233 ,  B23K35/26 ,  B23K35/262 ,  B23K35/268 ,  B23K35/28 ,  B23K35/40 ,  B23K2101/42 ,  B32B15/01 ,  B32B15/018 ,  C22C1/00 ,  C22C11/06 ,  C22C12/00 ,  C22C13/00 ,  C22C13/02 ,  C22C21/14 ,  H05K3/3463 ,  H05K2201/10992 ,  H05K2203/0405 ,  H05K2203/12 ,  Y10T428/12986

Abstract: When soldering a package having an electrode on which Ni/Au or Ag—Pd alloy is plated, to a printed circuit board having a Cu electrode or an electrode on which Cu is plated, a solid-phase diffusion layer is formed within a layered solder material for bonding different species of electrodes. The layered solder material is composed of a solder material of Sn—Ag—Cu series or Sn—Sb series and a solder material of Sn—Ag—Cu—Ni series or Sn—Pb series. The electrode on which Ni/Au or Ag—Pd alloy is plated and the Cu electrode or the electrode on which Cu is plated are soldered with the solder material of Sn—Ag—Cu series or Sn—Sb series being attached to the Cu electrode and the solder material of Sn—Ag—Cu—Ni series or Sn—Cu series being attached to the electrode on which Ni/Au or Ag—Pd alloy is plated. This restrains formation of intermetallic compounds and provides high bonding reliability.

Abstract translation: 当将具有Ni / Au或Ag-Pd合金的电极的封装焊接到具有Cu电极的印刷电路板或其上镀有Cu的电极时，在层状焊料内形成固相扩散层 用于粘合不同种类电极的材料。 层状焊料由Sn-Ag-Cu系或Sn-Sb系焊料，Sn-Ag-Cu-Ni系或Sn-Pb系焊料构成。 在其上镀有Ni / Au或Ag-Pd合金的电极和Cu电极或其上镀有Cu的电极与Sn-Ag-Cu系列或Sn-Sb系列的焊料材料焊接到Cu电极上 并且将Sn-Ag-Cu-Ni系或Sn-Cu系的焊料附着在镀Ni / Au或Ag-Pd合金的电极上。 这抑制了金属间化合物的形成，并提供了高粘结可靠性。

公开(公告)号：US20150282316A1

公开(公告)日：2015-10-01

申请号：US14543303

申请日：2014-11-17

Applicant: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD. ,  HON HAI PRECISION INDUSTRY CO., LTD.

Inventor： ZHANG-LONG PENG ,  CHUN-SHENG CHEN

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/09

CPC classification number: H05K1/111 ,  H05K1/09 ,  H05K1/181 ,  H05K3/3421 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/10242 ,  H05K2201/10992 ,  Y02P70/611

Abstract: A printed circuit board which avoids the melding of closely adjacent solders includes a top surface, a number of electronic elements and a number of solders. The top surface includes a plurality of copper clad areas. Each copper clad area includes a head area and a neck area. The neck area is positioned on same side of the head area. The neck area includes two edges extended from a fringe of the head area and a terminal point. The two edges intersect at the terminal point. The electronic elements are positioned at the head area. Each solder includes a soldering portion and a tip portion. The soldering portion is attached on the head area and surrounds the electronic element. The tip portion is attached on the neck area. A fringe of the solder is same as the fringe of the copper clad area.

Abstract translation: 避免紧密相邻的焊料熔接的印刷电路板包括顶表面，多个电子元件和多个焊料。 顶表面包括多个铜包覆区域。 每个铜包覆区域包括头部区域和颈部区域。 颈部区域位于头部区域的同一侧。 颈部区域包括从头部区域的边缘延伸的两个边缘和终点。 两个边缘在终点处相交。 电子元件位于头部区域。 每个焊料包括焊接部分和尖端部分。 焊接部分附着在头部区域上并围绕电子元件。 尖端部分附着在颈部区域。 焊料的边缘与铜包覆区域的边缘相同。

公开(公告)号：US08964402B2

公开(公告)日：2015-02-24

申请号：US13331105

申请日：2011-12-20

Applicant: Teru Nakanishi ,  Nobuyuki Hayashi ,  Masaru Morita ,  Yasuhiro Yoneda

Inventor： Teru Nakanishi ,  Nobuyuki Hayashi ,  Masaru Morita ,  Yasuhiro Yoneda

IPC: H05K7/00 ,  H05K1/11 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L2224/16 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K2201/09136 ,  H05K2201/10378 ,  H05K2201/10992 ,  Y02P70/613

Abstract: An electronic device includes a wiring board including a first electrode and a second electrode, a semiconductor device mounted on the wiring board and including a first terminal and a second terminal, an interposer provided between the wiring board and the semiconductor device, the interposer including a conductive pad and a sheet supporting the conductive pad, the conductive pad having a first surface on a side of the wiring board and a second surface on a side of the semiconductor device, a first solder connecting the first electrode positioned outside of an area in which the interposer is disposed with the first terminal positioned outside of the area, a second solder connecting the second electrode positioned inside of the area with the first surface of the conductive pad, and a third solder connecting the second terminal positioned inside of the area with the second surface of the conductive pad.

Abstract translation: 一种电子设备，包括：第一电极和第二电极的布线板;安装在所述布线板上的半导体器件，包括第一端子和第二端子，所述插入器设置在所述布线板和所述半导体器件之间，所述插入器包括： 所述导电焊盘和支撑所述导电焊盘的片材，所述导电焊盘具有在所述布线板的一侧上的第一表面和所述半导体器件的一侧上的第二表面;第一焊料，其将位于其中的所述第一电极的位于 所述插入件与所述第一端子位于所述区域的外侧，所述第二焊料将位于所述区域内的所述第二电极与所述导电焊盘的所述第一表面连接;以及第三焊料，其将位于所述区域内的所述第二端子与 导电垫的第二表面。

公开(公告)号：US08115110B2

公开(公告)日：2012-02-14

申请号：US11822137

申请日：2007-07-02

Applicant: Leon M. Khilchenko ,  Mark W. Gailus

Inventor： Leon M. Khilchenko ,  Mark W. Gailus

IPC: H05K1/11

CPC classification number: H05K3/4038 ,  H05K1/0298 ,  H05K3/321 ,  H05K3/3447 ,  H05K3/4046 ,  H05K3/4069 ,  H05K2201/0305 ,  H05K2201/0919 ,  H05K2201/10234 ,  H05K2201/1059 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/1446 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49165

Abstract: What is provided is a multi-layer PCB having a plurality of stacked dielectric layers, a conductor disposed on at least one of the plurality of dielectric layers, and a non-conductive via extending through at least a portion of the plurality of dielectric layers to intersect the conductor. A conductive body in an activated state is introduced into the non-conductive via, and upon contacting the conductor, the activated state conductive body adheres to the conductor. The activated state conductive body is then effected to a deactivated state, wherein the conductive body is affixed to the conductor to provide an electrical connection thereto.

Abstract translation: 提供的是具有多个堆叠的电介质层的多层PCB，设置在多个电介质层中的至少一个介质层上的导体，以及延伸穿过多个电介质层的至少一部分的非导电通孔， 与导体相交。 处于激活状态的导电体被引入到非导电通孔中，并且在与导体接触时，活化状态导电体粘附到导体。 然后使激活状态的导电体进入去激活状态，其中导电体固​​定到导体以提供与其的电连接。

公开(公告)号：US07968801B2

公开(公告)日：2011-06-28

申请号：US12011565

申请日：2008-01-25

Applicant: Kazuo Kinoshita

Inventor： Kazuo Kinoshita

IPC: H05K1/11

CPC classification number: H05K3/3436 ,  H05K3/3463 ,  H05K3/363 ,  H05K3/368 ,  H05K2201/094 ,  H05K2201/10234 ,  H05K2201/10992 ,  H05K2201/2036 ,  H05K2203/048 ,  Y02P70/613

Abstract: The camera module structure (10) of the present invention is arranged such that a board electrode (2) of a printed board (1) and a mounting electrode (4) of a camera module (3) mounted on the printed board (1) are joined with each other through a solder joint section (5), and the board electrode (2) and the mounting electrode (4) are aligned by self-alignment. The solder joint section (5) includes a solder section (16) for solder-joining, and a supporting section (17) for supporting the camera module (3). The present invention realizes a solder mounting structure wherein a heavy-weight component is joined on the board with solder by self-alignment.

Abstract translation: 本发明的摄像机模块结构（10）被布置成使得印刷板（1）的板电极（2）和安装在印刷板（1）上的相机模块（3）的安装电极（4） 通过焊接部分（5）彼此连接，并且板电极（2）和安装电极（4）通过自对准排列。 焊接部分（5）包括用于焊接的焊接部分（16）和用于支撑相机模块（3）的支撑部分（17）。 本发明实现了一种焊料安装结构，其中通过自对准将重量份的组分与焊料接合在板上。

公开(公告)号：US20110100690A1

公开(公告)日：2011-05-05

申请号：US12915786

申请日：2010-10-29

Applicant: Hideaki Yoshimura ,  Kenji Fukuzono ,  Takashi Kanda ,  Tomohisa Yagi ,  Hiroki Ikeda ,  Katsu Yanagimoto

Inventor： Hideaki Yoshimura ,  Kenji Fukuzono ,  Takashi Kanda ,  Tomohisa Yagi ,  Hiroki Ikeda ,  Katsu Yanagimoto

IPC: H05K1/02 ,  B32B15/08 ,  B23K35/12 ,  H01B1/02 ,  B23K31/02

CPC classification number: H05K3/4614 ,  H01B1/02 ,  H01B1/026 ,  H01L2224/16225 ,  H01L2924/01322 ,  H01L2924/01327 ,  H05K1/186 ,  H05K3/1216 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4069 ,  H05K3/4647 ,  H05K2201/0272 ,  H05K2201/09036 ,  H05K2201/10992 ,  Y10T428/31678 ,  H01L2924/00

Abstract: An electrically conductive body includes: a first electrically conductive material; a second electrically conductive material; and a bonding material bonding the first electrically conductive material to the second electrically conductive material at least for electric conduction. The bonding material is made of a metallic structure containing copper-tin based intermetallic compound phases and tin-bismuth phases, the copper-tin based intermetallic compound phases being continuous between the first electrically conductive material and the second electrically conductive material, the tin-bismuth phases being surrounded by the copper-tin based intermetallic compound phases.

Abstract translation: 导电体包括：第一导电材料; 第二导电材料; 以及至少用于导电的将第一导电材料接合到第二导电材料的接合材料。 接合材料由含有铜 - 锡基金属间化合物相和锡 - 铋相的金属结构制成，铜 - 锡基金属间化合物相在第一导电材料和第二导电材料之间连续，锡 - 铋 相被铜 - 锡基金属间化合物相包围。