公开(公告)号：US20170206171A1

公开(公告)日：2017-07-20

申请号：US15475718

申请日：2017-03-31

Applicant: Cavium, Inc.

Inventor： Shubhendu S. Mukherjee ,  Bryan W. Chin ,  Wilson P. Snyder, II ,  Michael Bertone ,  Richard E. Kessler ,  Christopher Mikulis

IPC: G06F12/1036 ,  G06F9/50 ,  G06F12/1009

CPC classification number: G06F12/1036 ,  G06F9/5077 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/651

Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.

公开(公告)号：US20170168926A1

公开(公告)日：2017-06-15

申请号：US15292583

申请日：2016-10-13

Applicant: International Business Machines Corporation

Inventor： Steven M. Partlow

IPC: G06F12/02 ,  G06F12/1036

CPC classification number: G06F12/023 ,  G06F3/0605 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/067 ,  G06F12/0223 ,  G06F12/0646 ,  G06F12/08 ,  G06F12/1036 ,  G06F12/12 ,  G06F17/3007 ,  G06F17/30233 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/50 ,  G06F2212/657

Abstract: Address-based thresholds for freemained frames are used to determine retention actions. Based, at least in part, on a comparison of a number of freemained frames for an address space against a threshold of freemained frames for the address space, freemained frames can be retained or rejected and/or the threshold can be adjusted.

公开(公告)号：US09678890B2

公开(公告)日：2017-06-13

申请号：US14867025

申请日：2015-09-28

Applicant: Intel Corporation

Inventor： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/02 ,  G06F9/455 ,  G06F12/0875 ,  G06F12/1045

CPC classification number: G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US09658792B2

公开(公告)日：2017-05-23

申请号：US14736849

申请日：2015-06-11

Applicant: International Business Machines Corporation

Inventor： Harris M. Morgenstern ,  Steven M. Partlow ,  Scott B. Tuttle ,  Elpida Tzortzatos

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/1036 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/4401 ,  G06F9/4403 ,  G06F12/023 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1044 ,  G06F2212/657 ,  G06F2212/68

Abstract: In one embodiment, a computer-implemented method includes receiving a large frame area (LFAREA) request, including a request for a plurality of page frame table entries (PFTEs) to back a plurality of frames in an LFAREA of main memory. Each of the plurality of frames has one of a first size and a second size, where the second size is larger than the first size. The method further includes counting how many frames in the main memory have yet to be initialized and have one of the first size and the second size. A size needed for the plurality of PFTEs is calculated, based at least in part on the counting. A storage area is reserved for the plurality of PFTEs, by a computer processor, where a size of the storage area is the size calculated based at least in part on the counting.

公开(公告)号：US20170116134A1

公开(公告)日：2017-04-27

申请号：US15396628

申请日：2016-12-31

Applicant: INTEL CORPORATION

Inventor： CHRISTOPHER D. BRYANT ,  RAMA S. GOPAL

IPC: G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F12/084 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/681 ,  G06F2212/684

Abstract: Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.

公开(公告)号：US5274789A

公开(公告)日：1993-12-28

申请号：US660486

申请日：1991-02-25

Applicant: Maria Costa ,  Carlo Leonardi

Inventor： Maria Costa ,  Carlo Leonardi

IPC: G06F12/02 ,  G06F12/1036 ,  G06F15/16 ,  G06F15/167 ,  G06F12/00

CPC classification number: G06F12/1036 ,  G06F12/0253 ,  G06F15/161 ,  G06F15/167

Abstract: Multiprocessor system having distributed shared resources and dynamical and selective global data replication in which a plurality of processors communicate each with the other through a sytem bus. Each CPU is provided with a local memory storing data used locally and global data shareable by a plurality of processes operative in differing CPUs and therefore replicated in the local memory of each CPU. The global data replication is performed, at page level, only when a global data page is effectively needed by a plurality of processes operative in differing CPUs and in those CPUs where the page is needed, the replication in the other CPUs being performed in a predetermined trash page of the local memory so that memory space required for replication is minimized, as is traffic on the system bus for global data replication and global data writes required for assuring global data consistency.

公开(公告)号：US20250126055A1

公开(公告)日：2025-04-17

申请号：US18989854

申请日：2024-12-20

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Robert Alverson ,  Partha Pratim Kundu ,  Duncan Roweth ,  David Charles Hewson ,  Albert SauPong Cheng

IPC: H04L45/28 ,  G06F9/50 ,  G06F9/54 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1045 ,  G06F13/14 ,  G06F13/16 ,  G06F13/28 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173 ,  H04L1/00 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/00 ,  H04L45/02 ,  H04L45/021 ,  H04L45/028 ,  H04L45/12 ,  H04L45/122 ,  H04L45/125 ,  H04L45/16 ,  H04L45/24 ,  H04L45/42 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/10 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/34 ,  H04L47/52 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275 ,  H04L47/629 ,  H04L47/76 ,  H04L47/762 ,  H04L47/78 ,  H04L47/80 ,  H04L49/00 ,  H04L49/101 ,  H04L49/15 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/28 ,  H04L69/40

Abstract: A network interface controller (NIC) capable of efficient packet forwarding is provided. The NIC can be equipped with a host interface, a packet generation logic block, and a forwarding logic block. During operation, the packet generation logic block can obtain, via the host interface, a message from the host device and for a remote device. The packet generation logic block may generate a plurality of packets for the remote device from the message. The forwarding logic block can then send a first subset of packets of the plurality of packets based on ordered delivery. If a first condition is met, the forwarding logic block can send a second subset of packets of the plurality of packets based on unordered delivery. Furthermore, if a second condition is met, the forwarding logic block can send a third subset of packets of the plurality of packets based on ordered delivery.

公开(公告)号：US12267229B2

公开(公告)日：2025-04-01

申请号：US17594521

申请日：2020-03-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Abdulla M. Bataineh ,  Timothy J. Johnson ,  Thomas L. Court ,  David Charles Hewson ,  Jonathan P. Beecroft ,  Joseph G. Kopnick

IPC: H04L47/10 ,  G06F9/50 ,  G06F9/54 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1045 ,  G06F13/14 ,  G06F13/16 ,  G06F13/28 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173 ,  H04L1/00 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/00 ,  H04L45/02 ,  H04L45/021 ,  H04L45/028 ,  H04L45/12 ,  H04L45/122 ,  H04L45/125 ,  H04L45/16 ,  H04L45/24 ,  H04L45/28 ,  H04L45/42 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/34 ,  H04L47/52 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275 ,  H04L47/629 ,  H04L47/76 ,  H04L47/762 ,  H04L47/78 ,  H04L47/80 ,  H04L49/00 ,  H04L49/101 ,  H04L49/15 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40 ,  H04L69/28

Abstract: Data-driven intelligent networking systems and methods are provided. The system can accommodate dynamic traffic with fast, effective endpoint congestion detection and control. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow can be acknowledged after reaching the egress point of the network, and the acknowledgement packets can be sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform flow control on a per-flow basis.

公开(公告)号：US12218828B2

公开(公告)日：2025-02-04

申请号：US17594638

申请日：2020-03-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Robert Alverson ,  Partha Pratim Kundu ,  Duncan Roweth ,  David Charles Hewson ,  Albert SauPong Cheng

IPC: H04L45/28 ,  G06F9/50 ,  G06F9/54 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1045 ,  G06F13/14 ,  G06F13/16 ,  G06F13/28 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173 ,  H04L1/00 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/00 ,  H04L45/02 ,  H04L45/021 ,  H04L45/028 ,  H04L45/12 ,  H04L45/122 ,  H04L45/125 ,  H04L45/16 ,  H04L45/24 ,  H04L45/42 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/10 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/34 ,  H04L47/52 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275 ,  H04L47/629 ,  H04L47/76 ,  H04L47/762 ,  H04L47/78 ,  H04L47/80 ,  H04L49/00 ,  H04L49/101 ,  H04L49/15 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/28 ,  H04L69/40

Abstract: A network interface controller (NIC) capable of efficient packet forwarding is provided. The NIC can be equipped with a host interface, a packet generation logic block, and a forwarding logic block. During operation, the packet generation logic block can obtain, via the host interface, a message from the host device and for a remote device. The packet generation logic block may generate a plurality of packets for the remote device from the message. The forwarding logic block can then send a first subset of packets of the plurality of packets based on ordered delivery. If a first condition is met, the forwarding logic block can send a second subset of packets of the plurality of packets based on unordered delivery. Furthermore, if a second condition is met, the forwarding logic block can send a third subset of packets of the plurality of packets based on ordered delivery.

公开(公告)号：US12132648B2

公开(公告)日：2024-10-29

申请号：US17594543

申请日：2020-03-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： David Charles Hewson ,  Partha Kundu

IPC: H04L45/28 ,  G06F9/50 ,  G06F9/54 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1045 ,  G06F13/14 ,  G06F13/16 ,  G06F13/28 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173 ,  H04L1/00 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/00 ,  H04L45/02 ,  H04L45/021 ,  H04L45/028 ,  H04L45/12 ,  H04L45/122 ,  H04L45/125 ,  H04L45/16 ,  H04L45/24 ,  H04L45/42 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/10 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/34 ,  H04L47/52 ,  H04L47/62 ,  H04L47/625 ,  H04L47/6275 ,  H04L47/629 ,  H04L47/76 ,  H04L47/762 ,  H04L47/78 ,  H04L47/80 ,  H04L49/00 ,  H04L49/101 ,  H04L49/15 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40 ,  H04L69/28

CPC classification number: H04L45/28 ,  G06F9/505 ,  G06F9/546 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1063 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/17331 ,  H04L1/0083 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/02 ,  H04L45/021 ,  H04L45/028 ,  H04L45/122 ,  H04L45/123 ,  H04L45/125 ,  H04L45/16 ,  H04L45/20 ,  H04L45/22 ,  H04L45/24 ,  H04L45/38 ,  H04L45/42 ,  H04L45/46 ,  H04L45/566 ,  H04L45/70 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/18 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/323 ,  H04L47/34 ,  H04L47/39 ,  H04L47/52 ,  H04L47/621 ,  H04L47/6235 ,  H04L47/626 ,  H04L47/6275 ,  H04L47/629 ,  H04L47/76 ,  H04L47/762 ,  H04L47/781 ,  H04L47/80 ,  H04L49/101 ,  H04L49/15 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9036 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40 ,  G06F2212/50 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L69/28

Abstract: A network interface controller (NIC) capable of efficient load balancing among the hardware engines is provided. The NIC can be equipped with a plurality of ordering control units (OCUs), a queue, a selection logic block, and an allocation logic block. The selection logic block can determine, from the plurality of OCUs, an OCU for a command from the queue, which can store one or more commands. The allocation logic block can then determine a selection setting for the OCU, select an egress queue for the command based on the selection setting, and send the command to the egress queue.