公开(公告)号：US20240154384A1

公开(公告)日：2024-05-09

申请号：US17982606

申请日：2022-11-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu ,  Koushik Ramachandran ,  Yusheng Bian

IPC: H01S5/0236 ,  H01S5/02251 ,  H01S5/024

CPC classification number: H01S5/0236 ,  H01S5/02251 ,  H01S5/024

Abstract: Structures for a cavity-mounted chip and methods of fabricating a structure for a cavity-mounted chip. The structure comprises a laser chip including a body attached to a substrate. The laser chip has an output, and the body of the laser chip has a bottom surface spaced from the substrate by a gap. The structure further comprises a first adhesive in the first gap and a second adhesive positioned in the first gap between the first adhesive and the output of the laser chip. The first adhesive has a first thermal conductivity, the second adhesive has a second thermal conductivity, and the first thermal conductivity of the first adhesive is greater than the second thermal conductivity of the second adhesive.

公开(公告)号：US20240145382A1

公开(公告)日：2024-05-02

申请号：US18051037

申请日：2022-10-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ravi P. Srivastava ,  Jagar Singh

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L28/10 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Disclosed is a structure and a method of forming the structure. The structure includes first and second semiconductor substrates with adjacent surfaces (e.g., bonded surfaces), a first spiral-shape metallic feature in the first semiconductor substrate, and a second spiral-shaped metallic feature in the second semiconductor substrate. The second spiral-shaped metallic feature is aligned above and electrically connected to the first spiral-shaped metallic feature. In some embodiments, the second spiral-shaped metallic feature is stacked on and immediately adjacent to the first spiral-shaped metallic feature at the bonded surfaces, thereby forming a relatively large inductor with high Qdc in a relatively small area. In other embodiments, the first and second spiral-shaped metallic features are discrete inductors located on opposite sides of the semiconductor substrates from the bonded surfaces but electrically connected in parallel (e.g., using stacked TSVs), effectively forming a relatively large inductor with a high Qdc in a relatively small area.

公开(公告)号：US20240142725A1

公开(公告)日：2024-05-02

申请号：US18050147

申请日：2022-10-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/42 ,  H01L31/0232 ,  H01L31/105

CPC classification number: G02B6/4203 ,  H01L31/02327 ,  H01L31/105

Abstract: Disclosed are embodiments of a photonic structure with at least one tapered coupler positioned laterally adjacent and along the length of a sidewall of a layer, such as a light absorption layer (LAL), of a photodetector to facilitate mode matching. Some embodiments include a vertically oriented photodetector, which is on an insulator layer and has an LAL stacked between bottom and top semiconductor layers, and a coupler, which is on the insulator layer positioned laterally adjacent to the photodetector and has stacked cores with one of the cores being at the same level as the LAL. Other embodiments include a horizontally oriented photodetector, which is on an insulator layer and has an LAL on a recessed section of a bottom semiconductor layer between side sections, and coupler(s), which is/are above side section(s) of the bottom semiconductor layer and, thus, positioned laterally adjacent to one or both sides of the LAL.

公开(公告)号：US11972999B2

公开(公告)日：2024-04-30

申请号：US17643023

申请日：2021-12-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark D. Levy ,  Rajendran Krishnasamy ,  Michael J. Zierak ,  Siva P. Adusumilli

IPC: H01L23/367 ,  H01L23/373 ,  H01L29/417 ,  H01L29/732

CPC classification number: H01L23/367 ,  H01L23/3736 ,  H01L29/41708 ,  H01L29/7325

Abstract: A structure includes an electrical device, and an active contact landed on a portion of the electrical device. The active contact includes a first body of a first material. A thermal dissipation pillar is adjacent the active contact and unlanded on but over the portion of the electrical device. The thermal dissipation pillar includes a second body of a second material having a higher thermal conductivity than the first material. The thermal dissipation pillar may be in thermal communication with a wire in a dielectric layer over the active contact and the thermal dissipation pillar. The electrical device can be any integrated circuit device that generates heat.

公开(公告)号：US20240136400A1

公开(公告)日：2024-04-25

申请号：US18405621

申请日：2024-01-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander Derrickson ,  Vibhor Jain ,  Judson R. Holt ,  Jagar Singh ,  Mankyu Yang

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/735 ,  H01L29/737

CPC classification number: H01L29/0821 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0817 ,  H01L29/1008 ,  H01L29/41708 ,  H01L29/735 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

公开(公告)号：US20240130255A1

公开(公告)日：2024-04-18

申请号：US18046170

申请日：2022-10-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Robert Viktor Seidel ,  Suk Hee Jang ,  Anastasia Voronova ,  Young Seon You

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1246 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/16

Abstract: The disclosure provides a structure and method for a memory element to confine a metal (e.g., a remaining portion of a metallic residue) with a spacer. A structure according to the disclosure includes a memory element over a first portion of an insulator layer. A portion of the memory element includes a sidewall over the insulator layer. A spacer is adjacent the sidewall of the memory element and on the first portion of the insulator layer. A metal-dielectric layer is within an interface between the spacer and the sidewall or an interface between the spacer and the first portion of the insulator layer. The insulator layer includes a second portion adjacent the first portion, and the second portion does not include the memory element, the spacer, and the metal-dielectric layer thereon.

公开(公告)号：US20240127868A1

公开(公告)日：2024-04-18

申请号：US18046961

申请日：2022-10-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Suresh Pasupula ,  Devesh Dwivedi ,  Chunsung Chiang

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/067 ,  G11C7/109 ,  G11C7/12

Abstract: Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

公开(公告)号：US20240120373A1

公开(公告)日：2024-04-11

申请号：US18045799

申请日：2022-10-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： HONG YU ,  DAVID PRITCHARD

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/0649 ,  H01L29/1066 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/66893 ,  H01L29/808

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first gate electrode, a second gate electrode, and an isolation structure. The first gate electrode is over the substrate and the second gate electrode is laterally adjacent thereto. The isolation structure is in contact with the first gate electrode and the second gate electrode.

公开(公告)号：US20240119974A1

公开(公告)日：2024-04-11

申请号：US18045529

申请日：2022-10-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

IPC: G11C7/10 ,  G11C7/12 ,  G11C13/00

CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/12 ,  G11C13/0069

Abstract: Disclosed structures include a partitioned memory architecture, which includes single resistor or dual resistor memory elements, which is configured for in-memory pipeline processing with minimal local IR drops, and which further includes additional circuitry to facilitate calibration processing. In some embodiments, the additional circuitry enables calibration processing when in-memory pipeline processing is paused. In these embodiments, the same bitlines and data sensing elements used for in-memory pipeline processing are also used for calibration processing. In other embodiments, the additional circuitry enables calibration processing concurrent with in-memory pipeline processing. In these embodiments, the additional circuitry includes duplicate pairs of memory elements with programmable resistors that can be connected to the operational circuitry for in-memory pipeline processing, to the calibration circuitry (including calibration-specific sense lines and sensing elements) for calibration processing, or to neither such that one memory element of the duplicate pair always remains operational allowing the other to undergo calibration.

公开(公告)号：US20240111088A1

公开(公告)日：2024-04-04

申请号：US17936939

申请日：2022-09-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Ryan William Sporer

IPC: G02B6/12 ,  G02B6/13

CPC classification number: G02B6/12004 ,  G02B6/13 ,  G02B2006/12061

Abstract: A structure or PIC structure includes a hybrid plasmonic (HP) waveguide. The HP waveguide includes a waveguide core, and a metal silicide layer contacting the waveguide core. The metal silicide layer replaces noble metals typically provided in hybrid plasmonic waveguides, providing improved optical signal containment characteristics. The metal silicide layer is also compatible with CMOS fabrication techniques, and capable of additional scaling with other CMOS structures. The HP waveguide also has a reduce form factor compared to conventional HP waveguides, providing room for more waveguides closer together.