中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

150 records (took 0.02 seconds)

    Vertical Transistor Component
    82.
    发明申请
    Vertical Transistor Component 有权
    垂直晶体管组件

    公开(公告)号：US20150214357A1

    公开(公告)日：2015-07-30

    申请号：US14682755

    申请日：2015-04-09

    Applicant: Infineon Technologies AG

    Inventor： Andreas Peter Meiser ,  Markus Zundel ,  Christoph Kadow

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/739

    CPC classification number: H01L29/7813 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7827

    Abstract: A vertical transistor component includes a semiconductor body with first and second surfaces, a drift region, and a source region and body region arranged between the drift region and the first surface. The body region is also arranged between the source region and the drift region. The vertical transistor component further includes a gate electrode arranged adjacent to the body zone, a gate dielectric arranged between the gate electrode and the body region, and a drain region arranged between the drift region and the second surface. A source electrode electrically contacts the source region, is electrically insulated from the gate electrode and arranged on the first surface. A drain electrode electrically contacts the drain region and is arranged on the second surface. A gate contact electrode is electrically insulated from the semiconductor body, extends in the semiconductor body to the second surface, and is electrically connected with the gate electrode.

    Abstract translation: 垂直晶体管组件包括具有第一和第二表面的半导体本体，漂移区以及布置在漂移区和第一表面之间的源区和体区。 身体区域也布置在源区域和漂移区域之间。 垂直晶体管部件还包括邻近体区设置的栅极电极，布置在栅极电极和主体区域之间的栅极电介质，以及布置在漂移区域和第二表面之间的漏极区域。 源电极与源区电接触，与栅电极电绝缘并且布置在第一表面上。 漏电极与漏极区域电接触并设置在第二表面上。 栅极接触电极与半导体本体电绝缘，在半导体本体中延伸到第二表面，并与栅电极电连接。

    Semiconductor Device Including Trench Transistor Cell Array and Manufacturing Method
    84.
    发明申请
    Semiconductor Device Including Trench Transistor Cell Array and Manufacturing Method 有权
    包括沟槽晶体管阵列和制造方法的半导体器件

    公开(公告)号：US20140327053A1

    公开(公告)日：2014-11-06

    申请号：US13886305

    申请日：2013-05-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Markus Zundel ,  Manfred Schneegans

    IPC: H01L29/04 ,  H01L21/8234 ,  H01L29/78

    CPC classification number: H01L29/045 ,  H01L21/823487 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

    Abstract: A semiconductor device includes a trench transistor cell array in a silicon semiconductor body with a first main surface and a second main surface opposite to the first main surface. A main lateral face of the semiconductor body between the first main surface and the second main surface has a first length along a first lateral direction parallel to the first and second main surfaces. The first length is equal or greater than lengths of other lateral faces of the semiconductor body. The trench transistor cell array includes predominantly linear gate trench portions. At least 50% of the linear gate trench portions extend along a second lateral direction or perpendicular to the second lateral direction. An angle between the first and second lateral directions is in a range of 45°±15°.

    Abstract translation: 半导体器件包括硅半导体本体中的沟槽晶体管单元阵列，其具有与第一主表面相对的第一主表面和第二主表面。 第一主表面和第二主表面之间的半导体本体的主侧面具有沿着平行于第一和第二主表面的第一横向方向的第一长度。 第一长度等于或大于半导体本体的其它侧面的长度。 沟槽晶体管单元阵列主要包括线性栅极沟槽部分。 至少50％的线性栅极沟槽部分沿着第二横向方向或垂直于第二横向方向延伸。 第一和第二横向之间的角度在45°±15°的范围内。

    Transistor Cell Array Including Semiconductor Diode
    85.
    发明申请
    Transistor Cell Array Including Semiconductor Diode 有权
    包括半导体二极管的晶体管单元阵列

    公开(公告)号：US20140167154A1

    公开(公告)日：2014-06-19

    申请号：US13716784

    申请日：2012-12-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Peter Nelle ,  Markus Zundel

    IPC: H01L27/088

    CPC classification number: H01L29/7808 ,  H01L27/0629 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7813 ,  H01L29/8613

    Abstract: One embodiment of a semiconductor device includes a dense trench transistor cell array. The dense trench transistor cell array includes a plurality of transistor cells in a semiconductor body. A width w3 of a transistor mesa region of each of the plurality of transistor cells and a width w1 of a first trench of each of the plurality of transistor cells satisfy the following relationship: w3

    Abstract translation: 半导体器件的一个实施例包括致密沟槽晶体管单元阵列。 密集沟槽晶体管单元阵列包括半导体本体中的多个晶体管单元。 多个晶体管单元的晶体管台面区域的宽度w3和多个晶体管单元中的每一个的第一沟槽的宽度w1满足以下关系：w3 <1.5×w1。 半导体器件还包括半导体二极管。 至少一个半导体二极管布置在多个晶体管单元的第一和第二部分之间，并且包括邻接第二沟槽的相对壁的二极管台面区域。 第一沟槽的深度d1和第二沟槽的深度d2相差至少20％。

    TEST METHOD AND TEST ARRANGEMENT
    86.
    发明申请
    TEST METHOD AND TEST ARRANGEMENT 有权
    测试方法和测试安排

    公开(公告)号：US20140097863A1

    公开(公告)日：2014-04-10

    申请号：US13647480

    申请日：2012-10-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： Markus Zundel ,  Franz Hirler ,  Peter Nelle

    IPC: G01R31/26

    CPC classification number: G01R31/2601 ,  G01R31/2884 ,  H01L22/32 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A test method in accordance with one or more embodiments may include: providing a semiconductor device to be tested, the semiconductor device including at least one device cell, the at least one device cell having at least one trench, at least one first terminal electrode region and at least one second terminal electrode region, at least one gate electrode, and at least one additional electrode disposed at least partially in the at least one trench, wherein an electrical potential of the at least one additional electrode may be controlled separately from electrical potentials of the at least one first terminal electrode region, the at least one second terminal electrode region and the at least one gate electrode; and applying at least one electrical test potential to at least the at least one additional electrode to detect defects in the at least one device cell.

    Abstract translation: 根据一个或多个实施例的测试方法可以包括：提供待测试的半导体器件，所述半导体器件包括至少一个器件单元，所述至少一个器件单元具有至少一个沟槽，至少一个第一端子电极区域 以及至少一个第二端子电极区域，至少一个栅极电极和至少部分地设置在所述至少一个沟槽中的至少一个附加电极，其中所述至少一个附加电极的电势可以与电势分开地控制 所述至少一个第一端子电极区域，所述至少一个第二端子电极区域和所述至少一个栅极电极; 以及向至少一个附加电极施加至少一个电测试电位以检测所述至少一个器件单元中的缺陷。

    Semiconductor device with a dopant source
    89.
    发明授权
    Semiconductor device with a dopant source 有权

    公开(公告)号：US11664416B2

    公开(公告)日：2023-05-30

    申请号：US16568911

    申请日：2019-09-12

    Applicant: Infineon Technologies AG

    Inventor： Markus Zundel

    IPC: H01L29/06 ,  H01L29/423 ,  H01L29/08

    CPC classification number: H01L29/0634 ,  H01L29/0847 ,  H01L29/4236

    Abstract: A semiconductor device includes a semiconductor body having a first surface. A first trench extends in a vertical direction into the semiconductor body. The semiconductor device also includes a first interlayer in the first trench and a first dopant source in the first trench. The first interlayer is arranged between the first dopant source and the semiconductor body, and the first dopant source includes a first dopant species. The semiconductor device also includes a semiconductor area doped with the first dopant species and which completely surrounds the first trench at least at a depth in the semiconductor body and adjoins the first trench.

    Semiconductor Device Including an Integrated Resistor
    90.
    发明申请
    Semiconductor Device Including an Integrated Resistor 审中-公开

    公开(公告)号：US20200152621A1

    公开(公告)日：2020-05-14

    申请号：US16744693

    申请日：2020-01-16

    Applicant: Infineon Technologies AG

    Inventor： Dirk Ahlers ,  Markus Zundel ,  Peter Brandl ,  Kurt Matoy ,  Thomas Ostermann

    IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06

    Abstract: A semiconductor device of an embodiment includes a transistor device in a semiconductor die including a semiconductor body. The transistor device includes transistor cells connected in parallel and covering at least 80% of an overall active area at a first surface of the semiconductor body. The semiconductor device further includes a control terminal contact area at the first surface electrically connected to a control electrode of each of the transistor cells. A first load terminal contact area at the first surface electrically connected to a first load terminal region of each of the transistor cells. The semiconductor device further includes a resistor in the semiconductor die and electrically coupled between the control terminal contact area and the first load terminal contact area, and a pn junction diode electrically connected in series with the resistor.

Patent Agency Ranking