公开(公告)号：US20240213169A1

公开(公告)日：2024-06-27

申请号：US18086265

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Yiqun Bai ,  Dingying Xu ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Kyle Jordan Arrington ,  Jeremy D. Ecton ,  Brandon C. Marin

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L23/64 ,  H10B80/00

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5382 ,  H01L23/5386 ,  H01L23/645 ,  H10B80/00 ,  H01L24/32

Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer including a cavity formed through the glass core layer; a glass core layer active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer; a second buildup layer contacting a second surface of the glass core layer; and a mold layer contacting a surface of the first buildup layer. The mold layer includes a mold layer active component die disposed in the mold layer, and the first buildup layer includes electrically conductive interconnect providing electrical continuity between the glass core layer active component die and the mold layer active component die. The top surface active component die is attached to the top surface of the substrate and electrically connected to the mold layer active component die.

公开(公告)号：US20240162191A1

公开(公告)日：2024-05-16

申请号：US18054211

申请日：2022-11-10

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Changhua Liu ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Mohammad Mamunur Rahman

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552

CPC classification number: H01L25/0655 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/552 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments of a package substrate includes: a conductive via in a first layer, the first layer comprising a positive-type photo-imageable dielectric; a conductive trace in a second layer, the second layer comprising a negative-type photo-imageable dielectric; and an insulative material between the first layer and the second layer, the insulative material configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers. The conductive via is directly attached to the conductive trace through the insulative material, the positive-type photo-imageable dielectric is soluble in a photoresist developer upon exposure to the electromagnetic radiation, and the negative-type photo-imageable dielectric is insoluble in the photoresist developer upon exposure to the electromagnetic radiation.

公开(公告)号：US20240113006A1

公开(公告)日：2024-04-04

申请号：US17937519

申请日：2022-10-03

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Gang Duan ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/14 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/16 ,  H01L25/0655 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/3841

Abstract: Embodiments of a microelectronic assembly comprise: an interposer structure of glass, a substrate comprising organic dielectric material, the substrate coupled to a first side of the interposer structure; and a plurality of IC dies. A first IC die in the plurality of IC dies is coupled to the substrate by first interconnects, a second IC die in the plurality of IC dies is embedded in the organic dielectric material of the substrate, the second IC die is coupled to the first IC die by second interconnects, the second IC die is coupled to the first side of the interposer structure by third interconnects, and a third IC die in the plurality of IC dies is coupled to a second side of the interposer structure by fourth interconnects, the second side of the interposer structure being opposite the first side of the interposer structure.

公开(公告)号：US20240111095A1

公开(公告)日：2024-04-04

申请号：US17957600

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Brandon C. Marin ,  Robert Alan May ,  Suddhasattwa Nad ,  Benjamin Duong

IPC: G02B6/122

CPC classification number: G02B6/1226

Abstract: A hybrid plasmonic waveguide and associated methods are disclosed. In one example, the electronic device includes combining an electromagnetic wave propagating in a waveguide with a high refractive index and a surface plasmon from a metal surface to create a hybrid plasmon wave in a low refractive index material separating the dielectric waveguide and metal surface. In selected examples, surface mounted hybrid plasmonic waveguides are shown. In selected examples hybrid plasmonic waveguides embedded in glass interposers are shown.

公开(公告)号：US11948848B2

公开(公告)日：2024-04-02

申请号：US16274091

申请日：2019-02-12

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Oscar Ojeda ,  Leonel Arana ,  Suddhasattwa Nad ,  Robert May ,  Hiroki Tanaka ,  Brandon C. Marin

IPC: H01L23/31 ,  H01L21/283 ,  H01L23/498 ,  H05K1/02 ,  H05K3/06

CPC classification number: H01L23/3114 ,  H01L21/283 ,  H05K1/0296 ,  H05K3/061

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.

公开(公告)号：US20240105625A1

公开(公告)日：2024-03-28

申请号：US17953511

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Darmawikarta ,  Benjamin Duong ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/17

Abstract: Disclosed herein are microelectronics package architectures utilizing open cavity interconnects for multi-die interconnect bridges and methods of manufacturing the same. The microelectronics packages may include a substrate, a first die, a solder resist layer, a first pad, and a bridge. The substrate may have a substrate surface. The solder resist layer may be connected to the substrate and may define an opening. The first pad may protrude from the substrate surface. The bridge may be located at least partially within the opening and in between the first die and the substrate. The bridge may include a first via that forms a first electrical pathway from the first pad to the first die.

公开(公告)号：US20240079337A1

公开(公告)日：2024-03-07

申请号：US17929471

申请日：2022-09-02

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Tchefor Ndukum ,  Kristof Kuwawi Darmawikarta ,  Sheng Li ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/49866 ,  H01L23/5381 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/16

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface, an opposing second surface, and lateral surfaces extending between the first and second surfaces; a conductive via coupled to the first surface of the conductive pad; a liner on the second surface and on the lateral surfaces of the conductive pad, wherein a material of the liner includes nickel, palladium, or gold; a microelectronic component having a conductive contact; and an interconnect electrically coupling the conductive contact of the microelectronic component and the liner on the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin.

公开(公告)号：US20240006291A1

公开(公告)日：2024-01-04

申请号：US17855961

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Jeremy D. Ecton ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Jason Steill ,  Yi Yang ,  Marcel Arlan Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49894 ,  H01L23/49816

Abstract: A substrate package comprises a substrate comprised of buildup layers. The substrate package can further include a passivating layer connected to the substrate and including a pocketed region. The pocketed region can include a first portion thinner than a second portion extending from the first portion. The substrate package can further include a solder ball encapsulated within the pocketed region. Other systems, apparatuses and methods are described.

公开(公告)号：US11855125B2

公开(公告)日：2023-12-26

申请号：US16560647

申请日：2019-09-04

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Brandon C. Marin ,  Jeremy Ecton ,  Hiroki Tanaka ,  Frank Truong

IPC: H01L21/48 ,  H01G4/008 ,  H01G4/28 ,  H01G4/12 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01G4/008 ,  H01G4/1209 ,  H01G4/28 ,  H01L21/4846

Abstract: Embodiments herein relate to a capacitor device or a manufacturing process flow for creating a capacitor that includes nanoislands within a package. The capacitor a first conductive plate having a first side and a second side opposite the first side and a second conductive plate having a first side and a second side opposite the first side where the first side of the first conductive plate faces the first side of the second conductive plate. A first plurality of nanoislands is distributed on the first side of the first conductive plate and a second plurality of nanoislands is distributed on the first side of the second conductive plate, where the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor. The nanoislands may be applied to the conductive plates using a sputtering technique.

公开(公告)号：US11737208B2

公开(公告)日：2023-08-22

申请号：US16268813

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Andrew James Brown ,  Rahul Jain ,  Dilan Seneviratne ,  Praneeth Kumar Akkinepally ,  Frank Truong

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H01L23/498

CPC classification number: H05K1/0228 ,  H01L23/49822 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.