公开(公告)号：US20170316880A1

公开(公告)日：2017-11-02

申请号：US15652002

申请日：2017-07-17

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Sasikanth Manipatruni ,  Shawna M. Liff ,  Vivek K. Singh

IPC: H01G4/008 ,  H01L29/06 ,  D03D1/00 ,  B82Y10/00 ,  H01G4/28 ,  H01L49/02 ,  H01L29/775

CPC classification number: H01G4/008 ,  B82Y10/00 ,  D03D1/0088 ,  D10B2401/18 ,  H01G4/28 ,  H01L28/60 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/775 ,  Y02E60/13

Abstract: A charge storage fiber is described. In an embodiment, the charge storage fiber includes a flexible electrically conducting fiber, a dielectric coating on the flexible electrically conducting fiber, and a metal coating on the dielectric coating. In an embodiment, the charge storage fiber is attached to a textile-based product.

公开(公告)号：US09775763B2

公开(公告)日：2017-10-03

申请号：US13719336

申请日：2012-12-19

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Brian S. Doyle ,  Ravindranath V. Mahajan

IPC: A61H1/02 ,  A61H3/00

CPC classification number: A61H1/024 ,  A61H1/0244 ,  A61H1/0266 ,  A61H1/0277 ,  A61H1/0281 ,  A61H1/0285 ,  A61H1/0288 ,  A61H1/0296 ,  A61H3/00 ,  A61H2201/1609 ,  A61H2201/1614 ,  A61H2201/1628 ,  A61H2201/1635 ,  A61H2201/164 ,  A61H2201/165 ,  A61H2201/5002 ,  A61H2201/501 ,  A61H2201/5097 ,  A61H2230/605

Abstract: Exoskeleton technology is described herein. Such technology includes but is not limited to exoskeletons, exoskeleton controllers, methods for controlling an exoskeleton, and combinations thereof. The exoskeleton technology may facilitate, enhance, and/or supplant the natural mobility of a user via a combination of sensor elements, processing/control elements, and actuating elements. User movement may be elicited by electrical stimulation of the user's muscles, actuation of one or more mechanical components, or a combination thereof. In some embodiments, the exoskeleton technology may adjust in response to measured inputs, such as motions or electrical signals produced by a user. In this way, the exoskeleton technology may interpret known inputs and learn new inputs, which may lead to a more seamless user experience.

公开(公告)号：US09741809B2

公开(公告)日：2017-08-22

申请号：US14856490

申请日：2015-09-16

Applicant: Intel Corporation

Inventor： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

IPC: H01L29/423 ,  H01L29/66 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/84

CPC classification number: H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US09577190B2

公开(公告)日：2017-02-21

申请号：US14752935

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Prashant Majhi ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Robert S. Chau

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

CPC classification number: H01L45/1293 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/0069 ,  G11C2013/008 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/128 ,  H01L45/141 ,  H01L45/144 ,  H01L45/146

Abstract: Heat-trapping bulk layers or thermal-boundary film stacks are formed between a heat-assisted active layer and an associated electrode to confine such transient heat to the active layer in a heat-assisted device (e.g., certain types of resistance-switching and selector elements used in non-volatile memory. Preferably, the heat-trapping layers or thermal-boundary stacks are electrically conductive while being thermally insulating or reflective. Heat-trapping layers use bulk absorption and re-radiation to trap heat. Materials may include, without limitation, chalcogenides with Group 6 elements. Thermal-boundary stacks use reflection from interfaces to trap heat and may include film layers as thin as 1-5 monolayers. Effectiveness of a thermal-boundary stack depends on the thermal impedance mismatch between layers of the stack, rendering thermally insulating bulk materials optional for thermal-boundary stack components.

Abstract translation: 在热辅助有源层和相关电极之间形成热捕获本体层或热边界膜堆，以将这种瞬态热量限制在热辅助装置中的有源层（例如，某些类型的电阻切换和选择器 在非易失性存储器中使用的元件优选地，热捕获层或热边界堆叠是导热的，同时是绝热或反射的。热捕获层使用大量吸收和再辐射来捕获热量，材料可以包括，没有 热边界堆叠使用界面的反射来捕获热量，并且可能包括薄至1-5单层的薄膜层。热边界堆叠的有效性取决于堆叠层之间的热阻抗失配 ，为热边界堆叠组件提供可选的绝热散装材料。

公开(公告)号：US09323327B2

公开(公告)日：2016-04-26

申请号：US13726078

申请日：2012-12-22

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Ravindranath V. Mahajan ,  Brian S. Doyle

IPC: G06F3/01 ,  G06F3/041 ,  G06F3/0481

CPC classification number: G06F3/016 ,  G06F3/014 ,  G06F3/0412 ,  G06F3/04812 ,  G06F3/0488

Abstract: A system and method for providing tactile feedback in a user interface. The system includes a tactile feedback assembly configured to communicate with a user interface of an electronic device. The tactile feedback assembly is configured to provide mechanical and/or nerve stimulation to a user during user interaction (e.g. navigation, input of data, etc.) of the user interface. The mechanical and/or nerve stimulation is configured to provide a user with tactile sensation (in the form of the sense of touch) in response to user interaction with the user interface, including, but not limited to, sense of texture and sense of pressure.

Abstract translation: 一种用于在用户界面中提供触觉反馈的系统和方法。 该系统包括被配置为与电子设备的用户界面通信的触觉反馈组件。 触觉反馈组件被配置为在用户界面的用户交互（例如，导航，数据输入等）期间向用户提供机械和/或神经刺激。 机械和/或神经刺激被配置为响应于用户与用户界面的交互而向用户提供触觉（以触觉的形式），包括但不限于纹理感和压力感 。

公开(公告)号：US20230223475A1

公开(公告)日：2023-07-13

申请号：US18174825

申请日：2023-02-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  Prashant Majhi ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L29/6684

Abstract: Disclosed herein are transistors with ferroelectric gates, and related methods and devices. For example, in some embodiments, a transistor may include a channel material, and a gate stack, and the gate stack may include a gate electrode material and a ferroelectric material between the gate electrode material and the channel material.

公开(公告)号：US11640839B2

公开(公告)日：2023-05-02

申请号：US17570249

申请日：2022-01-06

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Elijah V. Karpov

IPC: G11C11/22 ,  H01L27/11585

Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.

公开(公告)号：US20230086977A1

公开(公告)日：2023-03-23

申请号：US17477891

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Brian S. Doyle ,  Van H. Le ,  Abhishek A. Sharma

IPC: H01L27/088 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66

Abstract: Described herein are integrated circuit (IC) devices that include devices that include fin-based field-effect transistors (FinFETs) integrated over gate-all-around (GAA) transistors. The GAA transistors may serve to provide high-performance compute logic, and may be relatively low-voltage transistors, while FinFETs may be more suitable than GAA transistors for providing high-voltage transistors, and, therefore, may serve to provide peripheral logic for backend memory arrays implemented over the same support structure over which the GAA transistors and the FinFETs are provided. Such an arrangement may address the fundamental voltage incompatibility by integrating a mix of FinFETs and GAA transistors in stacked complimentary FET (CFET) architecture to enable embedded 1T-1X based memories.

公开(公告)号：US11233040B2

公开(公告)日：2022-01-25

申请号：US16629915

申请日：2017-09-25

Applicant: Intel Corporation

Inventor： Elijah V. Karpov ,  Prashant Majhi ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Yih Wang

IPC: H01L23/48 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: An embedded cross-point memory array is described. In an example, an integrated circuit structure includes a first die including a cross-point memory array comprising separate memory blocks, the memory blocks including orthogonally arranged conductive lines, and memory elements at cross-sections of the conductive lines. A first plurality of sockets is on the first die adjacent to the memory blocks, the first plurality of sockets comprising a first plurality of pads that connect to at least a portion to the conductive lines of the corresponding memory block. A second die includes logic circuitry and a second plurality of sockets comprising a second plurality of pads at least partially aligned with positions of the first plurality of pads on the first die. A top of the first die and a top of the second die face one another, wherein the first plurality of pads are bonded with the second plurality pads to directly connect the cross-point memory array to the logic circuitry.

公开(公告)号：US11195932B2

公开(公告)日：2021-12-07

申请号：US16650824

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Prashant Majhi ,  Ravi Pillarisetty ,  Elijah V. Karpov

IPC: H01L29/51 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L27/11 ,  H01L29/66

Abstract: In various embodiments disclosed herein are systems, methods, and apparatuses for using a ferroelectric material as a gate dielectric in an integrated circuit, for example, as part of a transistor. In an embodiment, the transistor can include a p-type metal oxide semiconductor (PMOS) transistor. In an embodiment, the transistor can have a p-doped substrate. In an embodiment, the channel of the transistor can be a p-doped channel. In an embodiment, the transistor having the ferroelectric material as the gate dielectric can be used in connection with an inverter. In an embodiment, the inverter can be used in connection with an static random access memory (SRAM) memory device.