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公开(公告)号：US20180120924A1
公开(公告)日：2018-05-03
申请号：US15668762
申请日：2017-08-04
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F11/0757 , Y02D10/126 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
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82.发明申请公开(公告)号：US20180060123A1
公开(公告)日：2018-03-01
申请号：US15252511
申请日：2016-08-31
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Israel Hirsh , Efraim Rotem , Doron Rajwan , Avinash N. Ananthakrishnan , Natanel Abitan , Ido Melamed , Guy M. Therien
IPC: G06F9/48
CPC classification number: G06F9/4893 , G06F1/32 , G06F9/48 , G06F9/4806 , G06F9/4843 , G06F9/485 , G06F9/4881 , G06F9/50 , G06F9/5005 , G06F9/5011 , G06F9/5016 , G06F9/5022 , G06F9/5027 , G06F9/5044 , G06F9/505 , G06F9/5094 , Y02D10/24
Abstract: In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.
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公开(公告)号：US09864667B2
公开(公告)日：2018-01-09
申请号：US14866584
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Doron Rajwan , Eliezer Weissmann , Yoni Aizik , Itai Feit , Tal Kuzi , Tomer Ziv , Nadav Shulman
CPC classification number: G06F11/3024 , G01V11/002 , G06F1/3228 , G06F1/324 , G06F9/5094 , G06F11/3058 , G06F11/3409 , G06F11/3419 , G06F11/3452 , G06F11/348 , G06F2201/88
Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.
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公开(公告)号：US09727345B2
公开(公告)日：2017-08-08
申请号：US13854001
申请日：2013-03-29
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Rinat Rappoport , Michael Mishaeli , Hisham Shafi , Oron Lenz , Jason W. Brandt , Stephen A. Fischer , Bret L. Toll , Inder M. Sodhi , Alon Naveh , Ganapati N. Srinivasa , Ashish V. Choubal , Scott D. Hahn , David A. Koufaty , Russell J. Fenger , Gaurav Khanna , Eugene Gorbatov , Mishali Naik , Andrew J. Herdrich , Abirami Prabhakaran , Sanjeev S. Sahagirdar , Paul Brett , Paolo Narvaez , Andrew D. Henroid , Dheeraj R. Subbareddy
CPC classification number: G06F9/4401 , G06F9/45558 , G06F9/5077 , G06F9/5094 , Y02D10/22 , Y02D10/36
Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.
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公开(公告)号：US09684541B2
公开(公告)日：2017-06-20
申请号：US14319099
申请日：2014-06-30
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Arik Gihon , Efraim Rotem , Paul S. Diefenbaugh , Eric C. Samson , Michael Mishaeli , Yoni Aizik , Chen Ranel
CPC classification number: G06F9/5044 , G06F3/14 , G06F9/5083 , G09G2360/08
Abstract: An apparatus and method for determining thread execution parallelism. For example, a processor in accordance with one embodiment comprises: a plurality of cores to execute a plurality of threads; a plurality of counters to collect data related to the execution of the plurality of threads on the plurality of cores; a dependency analysis module to analyze the data related to the execution of the threads and responsively determine a level of inter-thread dependency; and a control module to responsively adjust operation of the plurality of cores based on the determined level of inter-thread dependency.
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Patent Agency Ranking
公开(公告)号：US20170131754A1
公开(公告)日：2017-05-11
申请号：US14936945
申请日：2015-11-10
Applicant: Intel Corporation
Inventor： Shmuel Zobel , Maxim Levit , Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Dorit Shapira , Nadav Shulman
IPC: G06F1/26
CPC classification number: G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.
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87.发明申请公开(公告)号：US20170010656A1
公开(公告)日：2017-01-12
申请号：US15270208
申请日：2016-09-20
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Nadav Shulman , Alon Naveh , Hisham Abu-Salah
IPC: G06F1/32 , G06F12/0846
CPC classification number: G06F1/3275 , G06F1/28 , G06F1/3287 , G06F12/0802 , G06F12/084 , G06F12/0848 , G06F12/0864 , G06F2212/1028 , G06F2212/282 , G06F2212/502 , G06F2212/621 , Y02D10/13
Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明涉及具有多个核心的处理器和耦合到核心并且包括多个分区的高速缓冲存储器。 处理器还可以包括基于在至少一个核上执行的工作负载的存储器有界性来动态地改变高速缓存存储器的大小的逻辑。 描述和要求保护其他实施例。
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公开(公告)号：US20160349828A1
公开(公告)日：2016-12-01
申请号：US14722518
申请日：2015-05-27
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Efraim Rotem , Hisham Abu Salah , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Gal Leibovich , Yevgeni Sabin , Shay Levy
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/324 , G06F1/3243 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/171 , Y02D10/172
Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括：多个处理引擎，包括独立执行指令的第一处理引擎和第二处理引擎; 以及功率控制器，其包括用于控制所述处理引擎中的至少一个的性能状态的性能状态控制逻辑，以及用于在第一窗口中确定所述主动处理引擎的平均数量的第一逻辑，所述处理器的估计活动级别 并且至少部分地基于所估计的活动级别和所述第一窗口的比较来调整所述性能状态控制逻辑将执行性能状态确定和至少一个活动级别阈值的窗口长度中的至少一个 平均主动处理引擎数。 描述和要求保护其他实施例。
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公开(公告)号：US09471490B2
公开(公告)日：2016-10-18
申请号：US14840639
申请日：2015-08-31
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Eliezer Weissmann , Doron Rajwan , Nadav Shulman , Alon Naveh , Hisham Abu-Salah
CPC classification number: G06F1/3275 , G06F1/28 , G06F1/3287 , G06F12/0802 , G06F12/084 , G06F12/0848 , G06F12/0864 , G06F2212/1028 , G06F2212/282 , G06F2212/502 , G06F2212/621 , Y02D10/13
Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
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公开(公告)号：US09448829B2
公开(公告)日：2016-09-20
申请号：US13730491
申请日：2012-12-28
Applicant: Intel Corporation
Inventor： Paolo Narvaez , Ganapati N. Srinivasa , Eugene Gorbatov , Dheeraj R. Subbareddy , Mishali Naik , Alon Naveh , Abirami Prabhakaran , Eliezer Weissmann , Paul Brett , Scott D. Hahn , Andrew J. Herdrich , Gaurav Khanna , Russell J. Fenger , Bryant E. Bigbee , Andrew D. Henroid , David A. Koufaty
CPC classification number: G06F9/45558 , G06F9/3885 , G06F9/5077 , G06F2009/4557
Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.
Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：一组两个或更多个小物理处理器核; 至少一个大型物理处理器核具有相对较高性能的处理能力和相对较小的物理处理器核的相对较高的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将两个或更多个小物理处理器核心的集合暴露给软件，并从软件中隐藏至少一个大的物理处理器核心。
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