公开(公告)号：US10453679B2

公开(公告)日：2019-10-22

申请号：US15748619

申请日：2015-08-28

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Ravi Pillarisetty ,  Kimin Jun ,  Patrick Morrow ,  Valluri R. Rao ,  Paul B. Fischer ,  Robert S. Chau

IPC: H01L25/16 ,  H01L21/02 ,  H01L21/762 ,  H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L23/48 ,  H01L21/8258 ,  H01L27/085 ,  H01L21/18

Abstract: Methods and devices integrating circuitry including both III-N (e.g., GaN) transistors and Si-based (e.g., Si or SiGe) transistors. In some monolithic wafer-level integration embodiments, a silicon-on-insulator (SOI) substrate is employed as an epitaxial platform providing a first silicon surface advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N transistors (e.g., III-N HFETs) are formed, and a second silicon surface advantageous for seeding an epitaxial raised silicon upon which Si-based transistors (e.g., Si FETs) are formed. In some heterogeneous wafer-level integration embodiments, an SOI substrate is employed for a layer transfer of silicon suitable for fabricating the Si-based transistors onto another substrate upon which III-N transistors have been formed. In some such embodiments, the silicon layer transfer is stacked upon a planar interlayer dielectric (ILD) disposed over one or more metallization level interconnecting a plurality of III-N HFETs into HFET circuitry.

公开(公告)号：US10367070B2

公开(公告)日：2019-07-30

申请号：US15754804

申请日：2015-09-24

Applicant: Intel Corporation ,  Patrick Morrow ,  Mauro J. Kobrinsky ,  Kimin Jun ,  Il-Seok Son ,  Paul B. Fischer

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Kimin Jun ,  Il-Seok Son ,  Paul B. Fischer

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/417 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324

Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

公开(公告)号：US20190096917A1

公开(公告)日：2019-03-28

申请号：US16082260

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Rishabh Mehandru ,  Nathan D. Jack

IPC: H01L27/12 ,  H01L21/84 ,  H01L23/00 ,  H01L21/762 ,  H01L29/786

Abstract: Integrated circuit (IC) strata including one or more transistor and one or more semiconductor diode. A transistor may include one or more non-planar semiconductor bodies in which there is a channel region while the diode also includes one or more non-planar semiconductor bodies in which there is a p-type region, an n-type region, or both. One IC stratum may be only hundreds of nanometers in thickness and include both front-side and back-side interconnect levels. The front-side interconnect level is disposed over a front side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the transistor. The back-side interconnect level is disposed over a back side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the semiconductor diode.

公开(公告)号：US20180248012A1

公开(公告)日：2018-08-30

申请号：US15754804

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Kimin Jun ,  Il-Seok Son ,  Paul B. Fischer

IPC: H01L29/417 ,  H01L29/08 ,  H01L23/528 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L29/41791 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.

公开(公告)号：US20160133596A1

公开(公告)日：2016-05-12

申请号：US14997919

申请日：2016-01-18

Applicant: Intel Corporation

Inventor： Qing Ma ,  Jun He ,  Patrick Morrow ,  Paul B. Fischer ,  Sridhar Balakrishnan ,  Satish Radhakrishnan ,  Tatyana Andryushchenko ,  Guanghai Xu

IPC: H01L23/00 ,  H01L21/033

CPC classification number: H01L24/19 ,  B23K1/0016 ,  H01L21/0334 ,  H01L24/11 ,  H01L2224/245 ,  H01L2924/01322 ,  H01L2924/14 ,  H05K3/4015 ,  H05K2201/1028 ,  H01L2924/00

Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.

Abstract translation: 本主题涉及制造微电子器件的领域。 在至少一个实施例中，本主题涉及形成具有其部分的互连，其在附接到外部设备之后在冷却期间从微电子器件脱粘。 脱粘部分允许互连件弯曲并吸收应力。

公开(公告)号：US20160043056A1

公开(公告)日：2016-02-11

申请号：US14886452

申请日：2015-10-19

Applicant: INTEL CORPORATION

Inventor： Chia-Pin Chiu ,  Qing Ma ,  Robert L. Sankman ,  Paul B. Fischer ,  Patrick Morrow ,  William J. Lambert ,  Charles A. Gealer ,  Tyler Osborn

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/15 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/4803 ,  H01L21/561 ,  H01L21/568 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/2499 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A die assembly formed on a thin dielectric sheet is described. In one example, a first and a second die have interconnect areas. A dielectric sheet is over the interconnect areas of the first and the second die. Conductive vias in the dielectric sheet connect with pads of the interconnect areas. A build-up layer over the dielectric sheet includes routing to connect pads of the first die interconnect area to pads of the second die interconnect area through the conductive vias. The dies are mounted to a package substrate through the build-up layers, and a package cover is over the dies, the dielectric sheet, and the build-up layer.

Abstract translation: 描述了形成在薄介电片上的模具组件。 在一个示例中，第一和第二管芯具有互连区域。 电介质片在第一和第二管芯的互连区域之上。 电介质片中的导电孔与连接区的焊盘相连。 电介质片上的堆积层包括通过导电通孔将第一管芯互连区的焊盘连接到第二管芯互连区的焊盘的布线。 模具通过堆积层安装到封装衬底上，并且封装盖在模具，电介质层和堆积层之上。

公开(公告)号：US12288810B2

公开(公告)日：2025-04-29

申请号：US18415251

申请日：2024-01-17

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak ,  Kimin Jun

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/225 ,  H01L21/265

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20240332290A1

公开(公告)日：2024-10-03

申请号：US18129700

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Shao-Ming Koh ,  Patrick Morrow ,  Nikhil Mehta ,  Leonard Guler ,  Sudipto Naskar ,  Alison Davis ,  Dan Lavric ,  Matthew Prince ,  Jeanne Luce ,  Charles Wallace ,  Cortnie Vogelsberg ,  Rajaram Pai ,  Caitlin Kilroy ,  Jojo Amonoo ,  Sean Pursel ,  Yulia Gotlib

IPC: H01L27/088 ,  H01L21/033 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/088 ,  H01L21/0332 ,  H01L21/32139 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: Transistor structures comprising a gate electrode, or “gate,” that is self-aligned to underlying channel material. A mask material employed for patterning the channel material is further employed to define a cap of mask material having a larger width that protects a portion of gate material during a gate etch. The cap is therefore self-aligned to the channel material so that an amount by which a gate material extends laterally beyond the channel material is ensured to be symmetrical about a centerline of the channel material.

公开(公告)号：US20240331761A1

公开(公告)日：2024-10-03

申请号：US18126680

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Amlan Ghosh ,  Seenivasan Subramaniam ,  Patrick Morrow ,  Muhammad M. Khellah ,  Feroze Merchant

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  G11C11/4094

Abstract: An apparatus includes a first write bit line (WBL), a first P-channel metal oxide semiconductor (PMOS) transistor including a source coupled to the WBL, a first inverter including an input coupled to a drain of the first PMOS transistor, and a second PMOS transistor including a source coupled to an output of the first inverter. The first PMOS transistor and the second PMOS transistor are disposed in at least one PMOS layer configured between a first metal layer and a second metal layer. The register file circuit further includes a first via connecting a gate of the first PMOS transistor and a gate of the second PMOS transistor in the at least one PMOS layer to the first metal layer.

公开(公告)号：US12107085B2

公开(公告)日：2024-10-01

申请号：US18219374

申请日：2023-07-07

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Christopher Jezewski ,  Ehren Mannebach ,  Rishabh Mehandru ,  Patrick Morrow ,  Anand S. Murthy ,  Anh Phan ,  Willy Rachmady

IPC: H01L27/088 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8258 ,  H01L21/84 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/538 ,  H01L27/06 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/845 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L27/0924 ,  H01L24/94 ,  H01L2224/29188 ,  H01L2224/32145

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.