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    MEMS Fabrication Process with Two Cavities Operating at Different Pressures
    81.
    发明申请
    MEMS Fabrication Process with Two Cavities Operating at Different Pressures 有权
    具有两个工作在不同压力下的MEMS制造工艺

    公开(公告)号：US20150375995A1

    公开(公告)日：2015-12-31

    申请号：US14317101

    申请日：2014-06-27

    Applicant: Robert F. Steimle ,  Paul M. Winebarger

    Inventor： Robert F. Steimle ,  Paul M. Winebarger

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81C1/00238 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00246 ,  B81C1/00253

    Abstract: A method and apparatus are described for fabricating a high aspect ratio MEMS sensor device having multiple vertically-stacked inertial transducer elements (101B, 110D) formed in different layers of a multi-layer semiconductor structure (100) and one or more cap devices (200, 300) bonded to the multi-layer semiconductor structure (100) to protect any exposed inertial transducer element from ambient environmental conditions.

    Abstract translation: 描述了一种用于制造具有形成在多层半导体结构（100）和一个或多个盖装置（200）的不同层中的多个垂直堆叠的惯性换能器元件（101B，110D）的高纵横比MEMS传感器装置的方法和装置 ，300），其结合到多层半导体结构（100）以保护任何暴露的惯性换能器元件免受周围环境条件的影响。

    Vacuum Sealed MEMS and CMOS Package
    84.
    发明申请
    Vacuum Sealed MEMS and CMOS Package 有权
    真空密封MEMS和CMOS封装

    公开(公告)号：US20150329351A1

    公开(公告)日：2015-11-19

    申请号：US14137672

    申请日：2013-12-20

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chun-Wen Cheng ,  Yi-Chuan Teng ,  Hung-Chia Tsai ,  Chia-Hua Chu

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81C1/0023 ,  B81B7/007 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/096 ,  B81C1/00238 ,  B81C1/00301 ,  H01L21/76898 ,  H01L2224/11 ,  H01L2924/16235

    Abstract: A vacuum sealed MEMS and CMOS package and a process for making the same may include a capping wafer having a surface with a plurality of first cavities, a first device having a first surface with a second plurality of second cavities, a hermetic seal between the first surface of the first device and the surface of the capping wafer, and a second device having a first surface bonded to a second surface of the first device. The second device is a CMOS device with conductive through vias connecting the first device to a second surface of the second device, and conductive bumps on the second surface of the second device. Conductive bumps connect to the conductive through vias and wherein a plurality of conductive bumps connect to the second device. The hermetic seal forms a plurality of micro chambers between the capping wafer and the first device.

    Abstract translation: 真空密封的MEMS和CMOS封装及其制造方法可以包括具有多个第一腔的表面的封盖晶片，具有第二表面和第二多个第二腔的第一器件，第一和第二腔之间的密封 第一装置的表面和封盖晶片的表面，以及具有结合到第一装置的第二表面的第一表面的第二装置。 第二装置是CMOS器件，其具有将第一器件连接到第二器件的第二表面的导电通孔，以及在第二器件的第二表面上的导电凸块。 导电凸块连接到导电通孔，并且其中多个导电凸块连接到第二装置。 密封密封件在封盖晶片和第一装置之间形成多个微室。

    SEQUENTIAL WAFER BONDING
    85.
    发明申请
    SEQUENTIAL WAFER BONDING 有权
    顺序波形结合

    公开(公告)号：US20150321907A1

    公开(公告)日：2015-11-12

    申请号：US14804110

    申请日：2015-07-20

    Applicant: Philip H. Bowles ,  Stephen R. Hooper

    Inventor： Philip H. Bowles ,  Stephen R. Hooper

    IPC: B81B7/04 ,  B81B7/00

    CPC classification number: B81B7/04 ,  B81B7/0029 ,  B81B7/0041 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/012 ,  B81C1/0023 ,  B81C1/00293 ,  B81C2203/0145 ,  H01L23/10 ,  H01L29/66007 ,  H01L29/84 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Embodiments of a sensor device include a sensor substrate and a first cap substrate attached to the sensor substrate with a first bond material. The first bond material is arranged to define a first device cavity. A second cap substrate is attached to the sensor substrate with a second bond material. The second bond material is arranged to define a second device cavity. The second bond material has a lower bonding temperature than the first bond material. The second cap substrate is further secured to the sensor substrate by an adhesive material disposed between the sensor substrate and the second cap substrate.

    Abstract translation: 传感器装置的实施例包括传感器基板和附接到具有第一粘合材料的传感器基板的第一盖基板。 第一接合材料布置成限定第一器件腔。 用第二粘结材料将第二盖基片连接到传感器基板上。 第二接合材料被布置成限定第二器件腔。 第二粘合材料具有比第一粘结材料低的结合温度。 第二盖基板通过布置在传感器基板和第二盖基板之间的粘合材料进一步固定到传感器基板。

    Semiconductor device with through molding vias
    88.
    发明授权
    Semiconductor device with through molding vias 有权
    半导体器件具有通孔形成通孔

    公开(公告)号：US09150404B2

    公开(公告)日：2015-10-06

    申请号：US14107034

    申请日：2013-12-16

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chun-wen Cheng ,  Jung-Huei Peng ,  Shang-Ying Tsai ,  Hung-Chia Tsai ,  Yi-Chuan Teng

    IPC: H01L21/311 ,  B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/007 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2207/07 ,  B81B2207/094 ,  B81B2207/095 ,  B81C1/00301 ,  B81C2203/0154 ,  B81C2203/0771 ,  H01L21/568 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2924/18162

    Abstract: A method of forming a semiconductor device having through molding vias includes eutectic bonding a capping wafer and a base wafer to form a wafer package. The base wafer includes a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer includes a plurality of isolation trenches and a plurality of separation trenches having a depth greater than the isolation trenches with respect to a same surface of the capping wafer. The method also includes removing a portion of the capping wafer exposing a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. The method further includes separating the wafer package to separate the wafer package into a first chip package, a second chip package, and a third chip package.

    Abstract translation: 通过成型通孔形成半导体器件的方法包括共晶接合封盖晶片和基底晶片以形成晶片封装。 基底晶片包括第一芯片封装部分，第二芯片封装部分和第三芯片封装部分。 封盖晶片包括多个隔离沟槽和多个分离沟槽，其相对于封盖晶片的相同表面具有大于隔离沟槽的深度。 该方法还包括去除暴露第一芯片封装部分触点，第二芯片封装部分触点和第三芯片封装部分触点的封盖晶片的一部分。 该方法还包括分离晶片封装以将晶片封装分离成第一芯片封装，第二芯片封装和第三芯片封装。

    MEMS devices utilizing a thick metal layer of an interconnect metal film stack
    89.
    发明授权
    MEMS devices utilizing a thick metal layer of an interconnect metal film stack 有权
    使用互连金属膜叠层的厚金属层的MEMS器件

    公开(公告)号：US09150402B2

    公开(公告)日：2015-10-06

    申请号：US14127536

    申请日：2013-08-23

    Applicant: Rashed Mahameed ,  Kristen L. Dorsey ,  Mamdouh O. M M Abdelmejeed ,  Mohamed A. Abdelmoneum

    Inventor： Rashed Mahameed ,  Kristen L. Dorsey ,  Mamdouh O. M M Abdelmejeed ,  Mohamed A. Abdelmoneum

    IPC: H01L21/20 ,  B81B3/00 ,  B81C1/00

    CPC classification number: B81B3/0051 ,  B81B3/0021 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0145 ,  B81C1/00166 ,  B81C1/00246 ,  B81C1/00531 ,  B81C2203/0714 ,  B81C2203/0742 ,  G01C19/5733 ,  G01P15/125 ,  G01P2015/0814

    Abstract: A MEMS device, such as an accelerometer or gyroscope, fabricated in interconnect metallization compatible with a CMOS microelectronic device. In embodiments, a proof mass has a first body region utilizing a thick metal layer that is separated from a thin metal layer. The thick metal layer has a film thickness that is significantly greater than that of the thin metal layer for increased mass. The proof mass further includes a first sensing structure comprising the thin metal layer, but lacking the thick metal layer for small feature sizes and increased capacitive coupling to a surrounding fame that includes a second sensing structure comprising the thin metal layer, but also lacking the thick metal layer. In further embodiments, the frame is released and includes regions with the thick metal layer to better match film stress-induced static deflection of the proof mass.

    Abstract translation: MEMS器件，例如加速度计或陀螺仪，其制造在与CMOS微电子器件兼容的互连金属化中。 在实施例中，检验质量体具有利用与金属薄层分离的厚金属层的第一体区。 厚金属层的膜厚度明显大于金属层的厚度，以增加质量。 检测质量还包括第一感测结构，其包括薄金属层，但是缺少用于小特征尺寸的厚金属层和增加到周围声望的电容耦合，其包括包含薄金属层的第二感测结构，但是也缺少厚的 金属层。 在另外的实施例中，框架被释放并且包括具有较厚金属层的区域以更好地匹配膜应力引起的证明块的静态偏转。

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