公开(公告)号：US07271888B2

公开(公告)日：2007-09-18

申请号：US11029220

申请日：2005-01-03

Applicant: Uri Frodis ,  Adam L. Cohen ,  Michael S. Lockard

Inventor： Uri Frodis ,  Adam L. Cohen ,  Michael S. Lockard

IPC: G01N21/88

CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.

Abstract translation: 本发明的一些实施例提供了用于电化学制造多层结构（例如中尺度或微结构）的方法和装置，其具有改进的端点检测和用于在电化学制造过程中被平坦化的材料（例如层）的并行维护。 一些方法涉及在平坦化期间使用夹具，其确保材料的平面化平面平行于给定公差内的其它沉积平面。 一些方法涉及使用端点检测夹具，其相对于第一沉积层或相对于在制造过程期间形成的一些其它层，相对于衬底的初始表面确保沉积材料的精确高度。 在一些实施例中，平面化可以通过研磨发生，而其他实施例可以使用金刚石切片机。

公开(公告)号：US20050181316A1

公开(公告)日：2005-08-18

申请号：US11028944

申请日：2005-01-03

Applicant: Uri Frodis ,  Adam Cohen ,  Michael Lockard

Inventor： Uri Frodis ,  Adam Cohen ,  Michael Lockard

IPC: B05D1/38 ,  C08K3/00 ,  C25D3/30 ,  C25D3/38 ,  C25D3/48 ,  C25D5/02 ,  C25D5/10 ,  C25D21/12 ,  H01L21/288 ,  H01L21/301 ,  H01L21/302 ,  H01L21/4763 ,  H01L21/768

CPC classification number: C25D5/48 ,  B33Y10/00 ,  B81C1/00492 ,  B81C99/0065 ,  B81C2201/0104 ,  B81C2201/0197 ,  C25D1/00 ,  C25D1/003 ,  C25D5/022 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76885 ,  Y10T156/1052

Abstract: Some embodiments of the present invention provide processes and apparatus for electrochemically fabricating multilayer structures (e.g. mesoscale or microscale structures) with improved endpoint detection and parallelism maintenance for materials (e.g. layers) that are planarized during the electrochemical fabrication process. Some methods involve the use of a fixture during planarization that ensures that planarized planes of material are parallel to other deposited planes within a given tolerance. Some methods involve the use of an endpoint detection fixture that ensures precise heights of deposited materials relative to an initial surface of a substrate, relative to a first deposited layer, or relative to some other layer formed during the fabrication process. In some embodiments planarization may occur via lapping while other embodiments may use a diamond fly cutting machine.

公开(公告)号：US20030226604A1

公开(公告)日：2003-12-11

申请号：US10440515

申请日：2003-05-16

Applicant: MICRONIT MICROFLUIDICS B.V.

Inventor： Stefan Schlautmann ,  Albert Van den Berg ,  Johannes Gerardus Elisabeth Gardeniers

IPC: F15C001/04

CPC classification number: B81C1/00119 ,  B01L3/502707 ,  B01L2200/10 ,  B01L2300/0874 ,  B01L2300/0883 ,  B01L2300/0887 ,  B01L2400/0418 ,  B81B2201/0214 ,  B81B2201/058 ,  B81B2203/0338 ,  B81C2201/0104 ,  G01N33/48707 ,  Y10T137/2191

Abstract: The present invention relates to a method of fabricating a microfluidic device including at least two substrates provided with a fluid channel, comprising the steps of: a) etching at least a channel and one or more fluid ports in a first and/or a second substrate; b) depositing a first layer on a surface of the second substrate; c) partially removing the first layer in accordance with a predefined geometry; d) depositing a second layer on top of the first layer and the substrate surface; e) planarizing the second layer so as to smooth the upper surface thereof; f) aligning the first and second substrate; g) bonding the first substrate on the planarized second layer of the second substrate.

Abstract translation: 本发明涉及一种制造微流体装置的方法，该微流体装置包括具有流体通道的至少两个基板，包括以下步骤：a）至少蚀刻第一和/或第二基板中的通道和一个或多个流体端口 ; b）在第二基板的表面上沉积第一层; c）根据预定几何部分去除第一层; d）在第一层和衬底表面的顶部上沉积第二层; e）平面化第二层以平滑其上表面; f）对准所述第一和第二基板; g）将第一衬底接合在第二衬底的平坦化的第二层上。

公开(公告)号：US06642154B2

公开(公告)日：2003-11-04

申请号：US09900300

申请日：2001-07-05

Applicant: Jeffrey J. Peterson ,  Charles E. Hunt

Inventor： Jeffrey J. Peterson ,  Charles E. Hunt

IPC: H01L21302

CPC classification number: H01L21/30604 ,  B81C1/00626 ,  B81C2201/0104 ,  B81C2201/0133 ,  H01L21/30608

Abstract: One embodiment of the present invention provides a process for selective etching during semiconductor manufacturing. The process starts by receiving a silicon substrate with a first layer composed of a first material, which is covered by a second layer composed of a second material. The process then performs a first etching operation that etches some but not all of the second layer, so that a portion of the second layer remains covering the first layer. Next, the system performs a second etching operation to selectively etch through the remaining portion of the second layer using a selective etchant. The etch rate of the selective etchant through the second material is faster than an etch rate of the selective etchant through the first material, so that the second etching operation etches through the remaining portion of the second layer and stops at the first layer.

Abstract translation: 本发明的一个实施例提供了一种在半导体制造期间选择性蚀刻的方法。 该过程开始于接收由第一材料构成的第一层的硅衬底，第一层由第二材料构成的第二层覆盖。 然后，该过程执行蚀刻一些但不是全部第二层的第一蚀刻操作，使得第二层的一部分保持覆盖第一层。 接下来，系统执行第二蚀刻操作以选择性地使用选择性蚀刻剂蚀刻穿过第二层的剩余部分。 通过第二材料的选择性蚀刻剂的蚀刻速度比通过第一材料的选择性蚀刻剂的蚀刻速度快，使得第二蚀刻操作蚀刻穿过第二层的剩余部分并停止在第一层。

公开(公告)号：US06545299B1

公开(公告)日：2003-04-08

申请号：US10174625

申请日：2002-06-18

Applicant: Jeffrey J. Peterson ,  Charles E. Hunt

Inventor： Jeffrey J. Peterson ,  Charles E. Hunt

IPC: H01L31072

CPC classification number: B81C1/00611 ,  B24B37/013 ,  B24B37/042 ,  B81C2201/0104 ,  B81C2201/0123 ,  H01L21/30604 ,  H01L21/30608

Abstract: One embodiment of the present invention provides a process that uses selective etching to form a structure on a silicon substrate. The process starts by receiving the silicon substrate with a first layer composed of a first material, which includes voids created by a first etching operation. The process then forms a second layer composed of a second material over the first layer, so that the second layer fills in portions of voids in the first layer created by the first etching operation. Next, the process performs a chemo-mechanical polishing operation on the second layer down to the first layer so that only remaining portions of the second layer, within the voids created by the first etching operation, remain. The system then forms a third layer composed of a third material over the first layer and the remaining portions of the second layer, and performs a second etching operation using a selective etchant to remove the remaining portions of the second layer, thereby creating voids between the first layer and the third layer.

Abstract translation: 本发明的一个实施方案提供了使用选择性蚀刻在硅衬底上形成结构的方法。 该处理开始于接收硅衬底，第一层由第一材料构成，第一层包括由第一蚀刻操作产生的空隙。 然后，该过程在第一层上形成由第二材料构成的第二层，使得第二层填充由第一蚀刻操作产生的第一层中的空隙的部分。 接下来，该过程在第二层上进行到第一层的化学机械抛光操作，使得仅剩下由第一蚀刻操作产生的空隙内的第二层的剩余部分。 然后，该系统在第一层和第二层的其余部分上形成由第三材料组成的第三层，并且使用选择性蚀刻剂进行第二蚀刻操作以去除第二层的剩余部分，从而在第二层之间产生空隙 第一层和第三层。

公开(公告)号：US06465357B1

公开(公告)日：2002-10-15

申请号：US09900299

申请日：2001-07-05

Applicant: Jeffrey J. Peterson ,  Charles E. Hunt

Inventor： Jeffrey J. Peterson ,  Charles E. Hunt

IPC: H01L21311

CPC classification number: B81C1/00611 ,  B24B37/013 ,  B24B37/042 ,  B81C2201/0104 ,  B81C2201/0123 ,  H01L21/30604 ,  H01L21/30608

Abstract: One embodiment of the present invention provides a process that uses selective etching to form a structure on a silicon substrate. The process starts by receiving the silicon substrate with a first layer composed of a first material, which includes voids created by a first etching operation. The process then forms a second layer composed of a second material over the first layer, so that the a second layer fills in portions of voids in the first layer created by the first etching operation. Next, the process performs a chemo-mechanical polishing operation on the second layer down to the first layer so that only remaining portions of the second layer, within the voids created by the first etching operation, remain. The system then forms a third layer composed of a third material over the first layer and the remaining portions of the second layer, and performs a second etching operation using a selective etchant to remove the remaining portions of the second layer, thereby creating voids between the first layer and the third layer.

Abstract translation: 本发明的一个实施方案提供了使用选择性蚀刻在硅衬底上形成结构的方法。 该处理开始于接收硅衬底，第一层由第一材料构成，第一层包括由第一蚀刻操作产生的空隙。 然后，该过程在第一层上形成由第二材料组成的第二层，使得第二层填充由第一蚀刻操作产生的第一层中的空隙的部分。 接下来，该过程在第二层上进行到第一层的化学机械抛光操作，使得仅剩下由第一蚀刻操作产生的空隙内的第二层的剩余部分。 然后，该系统在第一层和第二层的其余部分上形成由第三材料组成的第三层，并且使用选择性蚀刻剂进行第二蚀刻操作以去除第二层的剩余部分，从而在第二层之间产生空隙 第一层和第三层。

公开(公告)号：US06242276B1

公开(公告)日：2001-06-05

申请号：US09482528

申请日：2000-01-14

Applicant: Seog-soon Baek ,  Byeoung-ju Ha ,  Young-soo Oh

Inventor： Seog-soon Baek ,  Byeoung-ju Ha ,  Young-soo Oh

IPC: H01L2100

CPC classification number: B81B3/0086 ,  B81B2201/0242 ,  B81B2203/0118 ,  B81C2201/0104 ,  B81C2201/0132

Abstract: A micro inertia sensor fabrication method in which thick silicon bonded to glass is processed at a high sectional ratio, is provided. In this method, silicon is bonded to a glass substrate, the bonded silicon is polished to have a desired thickness, a silicon structure is formed by etching the polished silicon using an RIE method, and the silicon structure is separated from the bottom by selectively etching glass below the silicon structure via grooves in etched silicon. Since the thick silicon bonded to glass is processed at a high sectional ratio, the area and thickness of the silicon to be measured are increased. Also, this method is simple since only one mask is used.

Abstract translation: 提供了以高截面比率处理结合到玻璃上的厚硅的微惯性传感器制造方法。 在该方法中，将硅结合到玻璃基板上，将接合的硅进行抛光以具有所需的厚度，通过使用RIE法蚀刻抛光的硅来形成硅结构，并且通过选择性蚀刻将硅结构与底部分离 通过蚀刻硅中的凹槽，在硅结构下面的玻璃。 由于结合到玻璃上的厚硅以高截面比进行处理，所以要测量的硅的面积和厚度增加。 此外，该方法很简单，因为只使用一个掩模。

公开(公告)号：US5429993A

公开(公告)日：1995-07-04

申请号：US216217

申请日：1994-03-21

Applicant: Bruce A. Beitman

Inventor： Bruce A. Beitman

IPC: G01P15/12 ,  B81B3/00 ,  G01P15/08 ,  H01L21/306 ,  H01L29/84 ,  H01L21/308

CPC classification number: B81C1/0015 ,  G01P15/0802 ,  B81B2201/0235 ,  B81B2203/0315 ,  B81C2201/0104 ,  B81C2201/0136 ,  B81C2201/019 ,  B81C2201/0191 ,  G01P2015/0828

Abstract: A semiconductor accelerometer is formed by attaching a semiconductor layer to a handle wafer by a thick oxide layer. Accelerometer geometry is patterned in the semiconductor layer, which is then used as a mask to etch out a cavity in the underlying thick oxide. The mask may include one or more apertures, so that a mass region will have corresponding apertures to the underlying oxide layer. The structure resulting from an oxide etch has the intended accelerometer geometry of a large volume mass region supported in cantilever fashion by a plurality of piezo-resistive arm regions to a surrounding, supporting portion of the semiconductor layer. Directly beneath this accelerometer geometry is a flex-accommodating cavity realized by the removal of the underlying oxide layer. The semiconductor layer remains attached to the handle wafer by means of the thick oxide layer that surrounds the accelerometer geometry, and which was adequately masked by the surrounding portion of the top semiconductor layer during the oxide etch step. In a second embodiment support arm regions are dimensioned separately from the mass region, using a plurality of buried oxide regions as semiconductor etch stops.

Abstract translation: 半导体加速度计是通过用厚的氧化物层将半导体层附着在手柄晶片上形成的。 加速度传感器几何形状在半导体层中图案化，然后将其用作掩模以蚀刻下面的厚氧化物中的空腔。 掩模可以包括一个或多个孔，使得质量区域将具有到下面的氧化物层的对应的孔。 由氧化物蚀刻产生的结构具有通过多个压阻臂区域以半悬臂方式支撑到半导体层的周围的支撑部分的大体积质量区域的预期加速度计几何形状。 直接在该加速度计几何形状之下的是通过去除下面的氧化物层而实现的柔性容纳腔。 半导体层通过围绕加速度计几何形状的厚氧化物层保持附着到处理晶片，并且在氧化物蚀刻步骤期间，半导体层被顶部半导体层的周围部分充分掩蔽。 在第二实施例中，使用多个掩埋氧化物区域作为半导体蚀刻停止件，将支撑臂区域与质量区域分开设计。